CMPE 212: Digital Analysis and Design LAB
Spring 2023, UMBC


The goals of the lab are
(1) To demonstrate the theory for a more integrated understanding of the subject.
(2) Introduction to the "Verilog" HDL(Hardware Description Language)

There is a discussion session followed by lab sessions each Friday. The description of the experiment(s) to be performed each week
will be released on this web-site by 5 pm on the Wednesday of that week.

If pre-lab exercises are specified in the lab description;   then those must be completed and submitted to the TA
prior to the start of the discussion session for that lab.

There are parts of each lab that are to be performed during the lab session and the results must be demonstrated to the TA in person.

Finally, if there is a post-lab component, then that is to be completed after the lab. By default you will have one week from the lab session date
to complete all the assignments/tasks/simulations in that lab exercise.

You should try and finish as much of your work as possible within the lab session(s) on the same day on which that lab is assigned and discussed.

Some labs are more involved and typically take longer than a week.
For those (longer) labs, the time you have to complete and submit will be specified
at the time the material for that lab is posted.

Lab 1: Introduction to the lab equipment: Multimeter, Power Supply, Resistors, and Breadboards

Lab 2: Integrated Circuits and Binary Code Conversion

Lab 3: Switching Expressions

Lab 4: DeMorgans Laws

Lab 5: Adders

Lab 6: The 7-Segment Display; Simultaneous minimization of Multiple switching functions using the Quine-McClusky Method.

The part of Lab 6 to be completed at home (Due on Friday 17 th March)

Lab 7 Addendum

In addition to the Verilog installation and running;
(the detailed instructions for those tasks are/will-be provided by the TA and Prof. Ryan Robucci)
this is the last part of lab 7.

Lab 8: SR-Latch.

Lab 9: Logic Hazards

Lab 10: Bidirectional Shift Register

Lab 11: State Machine Design and Implementation

Lab 12: State Machine Design Exercise 2: a simple vending machine
** Despite what the lab-write-up says, lab 12 is not a project.
Also, the name "coins to bills converter" is misleading, ignore it **
The machine you will design in this lab exercise is more like a simple candy dispensing/vending machine.
(Other than the bad title) the rest of the lab description is correct.

*** It turns out that the lab 12 description that was posted is WRONG ***
This was explained and discussed at length in class on Monday 8th May 2023
It was pointed out that VLSI level CAD tools or even architecture level CAD tools will not catch this type of glaring mistake in the design of a sequential machine.
For (a small amount of) extra credit: try to find out if there is a simulator/emulator that will catch this type of design flaw.

Obviously lab 12 is now canceled, you need not write reports for that lab. Those who already submitted reports will get (a small amount of) extra credit.

The last lab session time-slot on Friday 12th May 2023,   can be used to complete any prior labs
(from lab 1 to lab 11, in case anyone has not yet completed any of those previous experiments.)