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Course Information:

* Course Name: CMPE491N, Nanoelectronics for Computer Engineers
* Course Instructor: Reza M. Rad

Course Description:

The objective of this course is to provide the students with basic elements of the knowledge of emerging nanoelectronic devices. After an introduction to CMOS scaling and the coming challenges, the course will cover topics on main categories of nanoscale electronic components: carbon nanotube based devices, quantum dots and molecular devices. Basic electrical properties of these devices and their fabrication and characterization methods will be reviewed. More attention will be paid to the applications of these devices in implementation of future high performance digital systems, processing units and memories. Recently proposed memory and logic architectures that take advantage of the properties of the emerging devices will be discussed. Different defect tolerance approaches that are devised to deal with high defect rates in these components will also be addressed.

* Course Syllabus and Tentative Plan
* Introduction
* MOSFETs, a short review
* CMOS Process Steps
* CMOS Circuits Part I
* CMOS Circuits Part II
* CMOS Limits
* New Topics in MOSFETs
* Ferroelectric FETs
* Tunneling Devices I
* Tunneling Devices II
* Single Electron Devices
* Carbon Nanotubes
* A Defect Tolerant Computer Architecture
* Nanowire based Programmable Architectures
* NanoFabric Architecture

Announcements:

* The class location is changed to ITE 239 (October 18th)
* The first set of presentation will be due on Tuesday October 30th
* We will have the Midterm on Thursday November 1st
* I have provided the list of papers for second presentations. Please send me an email to let me know which paper you are choosing. Also let me know if you have problem finding the papers on internet. (You can find them through (UMBC-library -- Research port webpage) or directly on the web)


List of Papers for second presentations:

* NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
IEEE Design Automation Conference, 2006, Pages: 711 - 716
Authors : Wei Zhang, Niraj K. Jha , Li Shang
* CMOS-like logic in defective, nanoscale crossbars
Institute of Physics Publishing, Nanotechnology, vol 15, 2004 , Pages 881-891
Authors: G Snider , P. Kuekes and R Stanley Williams
* CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
Institute of Physics Publishing, Nanotechnology, vol 16, 2005 , Pages 888-900
Authors: D. Strukov , K Likharev
* Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test of Computers, 2005, Pages: 306 - 315
Authors : A DeHon , H. Naeimi
* Using Built-in Self Test and Adaptive Recovery for Defect Tolerance in Molecular Electronics-Based Nanofabrics
IEEE International Test Conference (ITC), 2005
Authors: Z. Wang , K. Chakrabarty
* Defect Tolerance at the End of Roadmap
IEEE International Test Conference (ITC), 2003 Pages: 1201- 1210
Authors: Mishra, M. Goldstein, S.C.
* CAEN-BIST: Testing the NanoFabric
IEEE International Test Conference (ITC), 2005 , Pages 462-471
Authors: J Brown , R. D. Blanton
* SCT: An Approach for Testing and Configuring Nanoscale Devices
IEEE VLSI Test Symposium, 2006
Authors: Rad, R.M.P. , Tehranipoor, M.
* A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), 2006, Page(s): 107-118
Authors: Rad, R.M.P. , Tehranipoor, M.
* Built-in Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics
IEEE Transactions on Computer Aided Design of Integrated Circuits, 2006
Authors: M. Tehranipoor and R. M. Rad

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