[Home][Research][Courses]

Publications:

Book Chapter

M. Tehranipoor and R. Rad, "Defect Tolerance for Reconfigurable Nanoscale Architectures",
in "Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability", by Mohammad Tehranipoor, Springer, 2007.


Journals

R. Rad and M. Tehranipoor, "SCT: A Novel Approach For Testing and Configuring Nanoscale Devices",
to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC), 2007.

R. Rad and M. Tehranipoor, "Evaluating Area and Performance of a Hybrid FPGA with Nanoscale Clusters and CMOS Routing",
to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC), 2007.

M. Tehranipoor and R. Rad, "Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, 943-958, May 2007.

Journals in Review

R.M. Rad and M. Tehranipoor, "Defect Tolerance through Avoiding Unknown Defects in Nanoscale Crossbar-based Devices",
submitted to IEEE Design \& Test Magazie

R. Rad and J. Plusquellic, "Deconvolution and Calibration of Power Pad Transients Signals for Fault Localization",

Conferences

R. M. Rad and Jim Plusquellic, "Temporal Analysis and Spatial Deconvolution of Power Pad Transients Signals for Fault Localization",
IEEE workshop on defect based testing (DBT'07), 2007.

R. M. Rad and M. Tehranipoor, "A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices",
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), pp. 107-115, 2006

R.M. Rad and M. Tehranipoor, "A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing",
in proc. of ACM IEEE Design Automation Conference (DAC), pp. 727-730, 2006.

R.M. Rad and M. Tehranipoor, "Investigating Test Time, Defect Map Size and Area for LUT and PLA-based Implementation of Nanoscale Devices",
IEEE North Atlantic Test Workshop , 2006.

R.M. Rad and M. Tehranipoor, "SCT: An Approach for Testing and Configuring Nanoscale Devices",
in proc. of IEEE VLSI Test Symposium (VTS’06), pp. 370-377, 2006.

M. Tehranipoor and R.M. Rad, "Fine-Grained Island Style Architecture for Molecular Electronic Devices",
in proc. of ACM/ SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'06), Poster, page 226, 2006.

M. Tehranipoor and R.M. Rad, "Test and Recovery for Fine-Grained Nanoscale Architectures",
in proc. of ACM/ SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'06), Poster, page 226, 2006.

G. R. Chaji, R. M. Pourrad, S. M. Fakhraie and M. H. Tehranipour, "eUTDSP: A Design Study of a New VLIW-Based DSP Architecture",
in proc. IEEE International Symposium on Circuits And Systems (ISCAS'03), Bangkok, Thailand, vol. 4, pp. 137-140, 2003.

 [Home][Research][Courses]