Instructor: Chintan Patel
Office: ITE 322
Office Hours: Mon & Wed, 4:00 PM - 5:30 PM or by appointment

Teaching Assistants:
Vrajesh Mistry : vmistry1@umbc.edu
Dhandeep Challagundla : vd58139@umbc.edu
Office Hours: TBD

Meeting Time and Location:Tues & Thrs, WEB, 4:00 - 5:15 PM
Lab Discussion: Fri, WEB/ITE375, 1:00 - 2:50 PM
Lab: Fri, WEB/ITE 375 (use according to instructions), 3:00 - 4:00 PM

Check regularly for important class information

 Syllabus posted.

 : May 3rd: IMPORTANT: Exam Details

Webex Link: Link for the exam

 Syllabus: Spring 2021 syllabus

 Lecture 1: Introduction

 Lecture 2: CMOS Basics I

 Lecture 3: CMOS Basics II

 Lecture 4: IC Technology

 Lecture 5: Circuit and System Representation

 Lecture 6: Quality Metrics I

 Lecture 7: Quality Metrics II

 Lecture 8: MOS Details

 Lecture 9: MOS Capacitance and Resistance Model

 Lecture 10: Inverter DC & AC Response

 Lecture 11: CMOS Fabrication I

 Lecture 12: CMOS Fabrication II

 Lecture 13: Circuit Characterization and Performance Estimation

 Lecture 14: Logical Effort

End of Exam Material

 Lecture 15: Power Dissipation

 Lecture 16: Interconnect and Wire Engineering

 Lecture 17: Design Margin, Reliability and Scaling

 Lecture 18: Combinational Logic Design

 Lecture 19: Combination Logic Design II

 Lab Submission

• Completely fill out and include the cover page (doc, html, pdf) with each lab submission.
• Labs will not be accepted without it.
• Late submission penalty is 20% lab grade per day late.
• Weekends will be considered as late days.

 Lab Assignment 1 (Due Mon Feb 15th): Structural VHDL

• Submit softcopy of the code and report (one pdf file), Use submit command. Class name: cmpe315_cpatel2 , Project name: lab1
• Code in the report: Use Enscript Command
• You have to submit a SINGLE pdf file instead of turning in a printed hard copy. It should include the lab cover page. Check the lab description for turning in your code

 Lab Assignment 2 (Due Mon Feb 22nd): Schematics and Spectre Simulations

 Lab Assignment 3 (Due Mon Mar 1st): Layout, Extraction and Simulations

• Layout Example Slides

 Lab Assignment 4 (Due Mon Mar 15th): D Flip-flop layout and simulations

 Lab Assignment 5 (Due Fri Apr 2nd): Import VHDL, layout and LVS

 Project Description

 Project Waveforms

 Example test benches and correct outputs

• Use tar -xvf filename to untar. Read the README.ncsim file in each directory for instructions
• Example Test Bench 1
• Example Test Bench 2

 Project Submission I Details (VHDL code & Report)

 Instructions for running VNC on ITE375 machines

 Instructions for running cadence tools

 DRC rules for AMI 0.6um technology

• Design Rules

 Cadence Incisive (VHDL) Tutorial

• Cadence VHLD Tutorial (NCVHDL)

 Cadence IC6 Tutorials

• Cadence Virtuoso Schematic Editor Tutorial
• Analog Design Environment Simulation Tutorial
• Cadence Virtuoso Layout Editor Tutorial

 Cadence IC5 Tutorials (OLD TOOLS, USE IC6 TUTORIALS)

• Cadence Virtuoso Schematic Editor Tutorial
• Analog Design Environment Simulation Tutorial
• Cadence Virtuoso Layout Editor Tutorial
• Cadence Virtuoso Extraction Tutorial (.avi movie file)
• Cadence SpectreS Simulation Tutorial (.avi movie file)
• Cadence Waveform Browser Tutorial (.avi movie file)
• Cadence VHLDIN Tutorial (Importing structural VHDL)

 VHDL Help

• Intro to VHDL
• A Simple VHDL Example: Inverter
  • Inverter VHDL description : inverter.vhdl
  • Inverter Test File (using input/output files): inverter_test.vhdl
  • Inverter Input File (for use with inverter_test.vhdl): inverter_in.txt
  • Inverter Output File (output from inverter_test.vhdl): inverter_out.txt
  • NCSIM run file (for use with inverter_test.vhdl): inverter_ncsim.run
  • Inverter Test File (output on stdout/screen): inverter_test_stdout.vhdl
  • NCSIM run file (for use with inverter_test_stdout.vhdl): inverter_ncsim_stdout.run
• Structural VHDL Example: 4-bit Ripple Carry Adder
  • Adder VHDL description : adder4.vhdl
  • Adder Test File (using input/output files): adder4_test.vhdl
  • Adder Input File (for use with adder4_test.vhdl): adder4_in.txt
  • Adder Output File (output from adder4_test.vhdl): adder4_out.txt
  • NCSIM run file (for use with adder4_test.vhdl): adder4_ncsim.run
  • To run the stdout version testfile below use the -v93 option with ncvhdl and ncelab
  • Adder Test File (output on stdout/screen): adder4_test_stdout.vhdl
  • NCSIM run file (for use with adder4_test_stdout.vhdl): adder4_ncsim_stdout.run
• Transmission Gate VHDL code
• Negative Edge Triggered D Flip Flop VHDL code
• Positive Level Sensitive Larch VHDL Code
• Useful VHDL information and links: Do not use the cadence VHDL setup information on this site. Use what we discussed in class (as given in the tutorial)