PJRC.COM Offline Archive, February 07, 2004
Visit this page on the live site

skip navigational linksPJRC
Shopping Cart Checkout Shipping Cost Download Website
Home MP3 Player 8051 Tools All Projects PJRC Store Site Map
You are here: OSU8 Microprocessor Schematic OSU8 Core Control State Machine Sheet 8 Search PJRC

OSU8 Microprocessor
Overview
CPU Programming
Hardware Info
Schematic
Implementation
Download Files

Control State Machine, Sheet #8

This one of several schematics that make up the control logic. This schematic was generated automatically by logic synthesis, driven by the logic spec generated from the microcode, by the microcode compiler. Together with the 6 bit state register this logic makes up control state machine that causes the OSU8 microprocessor to execture code.

(7) Previous Schematic Sheet

Also, view a much larger and more readable version

Schematic Drawing


OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/c4r.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>
Return to OSU8 Main Schematic

Complete List of All OSU8 Schematics