PJRC.COM Offline Archive, February 07, 2004
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OSU8 Microprocessor
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CPU Programming
Hardware Info
Schematic
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Address Decode

This little circuit provides some simple address decoding, which would normally be implemented by a logic circuit on the circuit board. Because this design was implemented in a Xilinx FPGA chip, adding a bit of extra logic was easier than putting another chip on the board. The test board has three chips, a Flash ROM (which also contains the FPGA configuration bits), SRAM, and a UART.

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/addr_sec.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>
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