OSU8 Xilinx Implementation
This top-level schematic represents the OSU8 implementation in
a Xilinx FPGA chip. Click on the OSU8 Core
block to see the OSU8 main schematic.
Thoughout these schematics, the
green blocks are links to their
lower level schematics.
Individual gates and flip-flops do not have schematics under them,
because they are the primitive elements for Xilinx place-and-route,
and for the ViewSim gate-level simulation.
Lower Schematics
OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/osu8chip.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions:
<paul@pjrc.com>
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Schematic
CPU Programming