OSU8 Microprocessor

PJRC.COM Offline Archive, February 07, 2004
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You are here: OSU8 Microprocessor Schematic OSU8 Core Control State Machine Sheet 2 Search PJRC

OSU8 Microprocessor

Overview
CPU Programming
Hardware Info
Schematic

Xilinx Implementation
Address Decoder
OSU8 Core

Normal Size
Large Size
8-Bit Data ALU
16-Bit Addr ALU
Control State Machine

Sheet 1
Sheet 2
Sheet 3
Sheet 4
Sheet 5
Sheet 6
Sheet 7
Sheet 8
Large Copy

State Register
Bus Control
Accumulator
B Register
Status Bits
Operand Register
Program Counter
Stack Pointer
P1 Pointer
P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers

Full Hierarchy Index

Implementation
Download Files

Control State Machine, Sheet #2

This one of several schematics that make up the control logic. This schematic was generated automatically by logic synthesis, driven by the logic spec generated from the microcode, by the microcode compiler. Together with the 6 bit state register this logic makes up control state machine that causes the OSU8 microprocessor to execture code.

(1) Previous Schematic Sheet

Next Schematic Sheet (6)

Also, view a much larger and more readable version

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/c2l.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>

Return to OSU8 Main Schematic

Complete List of All OSU8 Schematics