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List of Publications of CADT Research Group
    2006
  1. M. Tehranipoor and R. M.P. Rad, “Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics,” to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), 2006
  2. D. Acharyya, A. Singh, M. Tehranipoor, C. Patel and J. Plusquellic, “Test Chip Results Investigating Defect Sensitivity of Quiescent Signal Analysis: a Multiple Supply Pad IDDQ Method,” to appear in IEEE Design and Test of Computers, 2006.
  3. R. M. Rad and M. Tehranipoor, “A Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing,” to appear in Design Automation Conference (DAC’06), 2006.
  4. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” to appear in Design Automation Conference (DAC’06), 2006.
  5. R. M. Rad and M. Tehranipoor, “Test Time and Defect Map Analysis of PLA and LUT-Based Nano-Architectures,” in Proc. of IEEE North Atlantic Test Workshop (NATW’06), 2006.
  6. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Case Study of IR-Drop Effects During Faster-than-at-Speed Delay Test,” in Proc. of IEEE North Atlantic Test Workshop (NATW’06), 2006.
  7. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results,” in Proc. of IEEE North Atlantic Test Workshop (NATW’06), 2006.
  8. J. Lee, N. Ahmed, M. Tehranipoor, V. Jayaram and J. Plusquellic, “A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG,” in Proc. of IEEE North Atlantic Test Workshop (NATW’06), 2006.
  9. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and K. Butler, “Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers,” to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), 2006.
  10. R. M. Rad and M. Tehranipoor, “SCT: An Approach for Testing and Configuring Nanoscale Devices,” to appear in IEEE VLSI Test Symposium (VTS’06), 2006.
  11. J. Lee, M. Tehranipoor and J. Plusquellic, “A Low-Cost Solution for Protecting IPs Against Side-Channel Scan-Based Attacks,” in Proc. of IEEE VLSI Test Symposium (VTS’06), 2006.
  12. R. M. P. Rad and M. Tehranipoor, “Fine-Grained Island Style Architecture for Molecular Electronic Devices,” International Symposium on Field-Programmable Gate Arrays (FPGA'06) (Poster).
  13. M. Tehranipoor and R. M. P. Rad, “Test and Recovery for Fine-Grained Nanoscale Architectures,” International Symposium on Field-Programmable Gate Arrays (FPGA'06) (Poster).
    14. 2005
  14. C.P. Ravikumar, N. Ahmed and M. Tehranipoor, “Practicing Transition-Fault Testing with Physical-Design-Friendly Flows,” Texas Instruments India Technical Conference (TIITC’05), 2005.
  15. M. Tehranipoor, M. Nourani and K. Chakrabarty, "Nine-Coded Compression Technique for Testing Embedded Cores in SoCs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 6, pp. 719-731, June 2005.
  16. M. Nourani and M. H. Tehranipour, “RL-Huffman Encoding for Test Compression and Power Reduction in Scan Application,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, no. 1, pp. 91-115, Jan. 2005.
  17. M. ElShoukry, C.P. Ravikumar and M. Tehranipoor, "Partial Gating Optimization for Power Reduction During Test Application," in Proc. of IEEE 14th Asian Test Symposium (ATS'05), 2005.
  18. M. Tehranipoor, M. Nourani and N. Ahmed, "Low Transistion LFSR for BIST-Based Applications," in Proc. of IEEE 14th Asian Test Symposium (ATS'05), 2005.
  19. C.P. Ravikumar, N.Ahmed and M. Tehranipoor, "Practicing Transistion-Fault Testing with Physical-Design-Friendly Flows," Texas Instruments India Technical Conference (TIITC'05), 2005.
  20. J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, " Securing Scan Design Using Lock & Key Technique," in Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
  21. N. Ahmed and M. Tehranipoor, "Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique," in Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
  22. M. Tehranipoor, "Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure," in Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
  23. M. Alisafaee, S. M. Fakhraie and M. Tehranipoor, "Architecture of an Embedded Queue Management Engine for High-Speed Network Devices," in IEEE MidWest Symposium on Circuits and Systems (MWSCAS'05), 2005.
  24. H. Esmaeilzadeh, F. Farzan, N. Shahidi, S. M. Fakhraie, C. Lucas and M. Tehranipoor, "NnSP: Embedded Neural Networks Stream Processor," in IEEE MidWest Symposium on Circuits and Systems (MWSCAS'05), 2005.
  25. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, "Addressing At-speed Fault Coverage and Test Cost Issues Using Enhanced Launch-off-Capture," Texas Instruments Symposium on Test (TIST'05), 2005.
  26. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, "At-Speed Local Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers," Texas Instruments Symposium on Test (TIST'05), 2005.
  27. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, "Enhanced Launch-off-Capture Transition Fault Testing," in Proc. of IEEE International Test Conf. (ITC'05), 2005.
  28. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and J. Plusquellic, "At-Speed Transition Fault Testing Using Low Speed Testers With Application to Reduced Scan Enable Routing Area," IEEE North Atlantic Test Workshop (NATW'05), pp. 112-119, 2005.
  29. D. Acharyya, A. Singh, M. Tehranipoor, C. Patel and J. Plusquellic, "Sensitivity Analysis of Quiescent Signal Analysis for Defect Detection," IEEE. Int. Workshop on Defect Based Testing (DBT'05), pp. 3-10, 2005.
  30. M. Nourani, M. Tehranipoor and N. Ahmed, "Pattern Generation and Estimation for Power Supply Noise Analysis," in proc. IEEE VLSI Test Symposium (VTS'05), pp. 439-444, 2005.
  31. N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, "At-Speed Transition Fault Testing With Low Speed Scan Enable," in proc. IEEE VLSI Test Symposium (VTS'05), pp. 42-47, 2005.
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