As CMOS technology for implementing digital integrated circuits continues to scale down it will face theoretical and also economical difficulties. Emerging technologies to overcome these obstacles are growing up in different fields. One of strongest threads of research in this area is based on using chemically created nano-scale devices like molecular switches, nanowires, nanotubes and nano-FETs in digital circuits. Limitations in assembly technology of these devices results in only regular structures like arrays. So designers will have to use these regular structure to design their architectures.

These emerging technologies also face another limitation. High defect densities are expected in them. So, suggested designs must be highly defect tolerant and testable. As design of architectures based on these technology develops, need for appropriate CAD tools in this field becomes obvious. Since the design paradigm in these technologies will be completely different in terms of architecture and device, proper CAD tools at all levels of abstraction will be required. This project focuses on Architecture, Test and CAD issues on emerging nano technologies. The aim here is to search and try to find solutions to the wide range of problems in each of these fields.

Security has become a greater concern in the design and test of chips recently. This has become more apparent with the advent of cryptochips. Cryptochips perform encryption and decryption algorithms at the circuit level. Many researchers have been able to show that these chips are highly vulnerable to various power analysis, timing, and fault-injection attacks if not specifically designed with countermeasures in mind. If not considered carefully, strong encryption algorithms that would take years to crack by brute force can otherwise be crippled in a manner of weeks, days, or even hours through these side-channel attacks.

Currently, the main objective in testing has been to control and observe a chip as much as possible in order to achieve high fault coverage and diagnosis on the CUT. As useful as these properties are for testing, they are completely contradictory to the objectives of security on a chip. In order to protect a chip from malicious users, a chip must reveal as little as possible while still considered useful to the end-user, but for reliability, a test engineer needs as much access to the chip as possible. Recently, scan test has been proven a security risk to the intellectual property (IP) on the chip. Some researchers were able to simulate an attack on the scan chain of a DES cryptochip to reveal the secret key with using only three plaintexts. Although the scan chains have only been exploited to find the secret key of a cryptochip, it is just as easy to uncover proprietary intellectual property through scan chains. Vital registers are part of the scan chains that are allowing high controllability and observability. This amount of access has been shown to reveal a lot more than the fabrication defects in a chip. In order to prevent IP theft, security measures must be implemented during the design phase.

With today’s design size in millions of gates and working frequency in gigahertz range, timing-related defects constitute a large proportion of the defect population, and at-speed test is crucial. Transition and path delay fault testing together provide a good coverage for delay-induced defects. The transition fault model (TFM) is widely practiced in the industry since it leads to manageable number of faults. There are two transition fault pattern generation methods, namely launch-off-last-shift (LOS) and launch-off-capture (LOC). In LOS, the scan enable signal SEN must change at-speed. In LOC, the at-speed constraint on the SEN signal is relaxed and dead cycles are added after the last shift to provide enough time for SEN to settle low. LOS provides higher fault coverage with lower number of patterns compared to LOC. The LOC technique is based on a sequential ATPG algorithm while the LOS method uses a combinational ATPG algorithm. This will increase the test pattern generation time in case of LOC and a high fault coverage cannot be guaranteed. The main limitation for practice of LOS is that it requires the SEN signal to be timing critical and is not applicable on low cost testers. As the flop count increases, the SEN fanout becomes excessive and routing area increases dramatically. Considering thousands of flip-flops in today’s large designs, implementation of an at-speed SEN in case of LOS can be as costly as a clock synthesis. In contrast, LOC is easier to implement using low cost testers due to its independency on the at-speed SEN signal; however it provides lower test coverage. Other major challenges for both LOC and LOS methods are as follows: the routing area must be decreased and the test coverage must be increased to ensure test quality.

The power supply noise (PSN) reduces the actual voltage level reaching a device, which increases the signal delay and results in signal integrity loss and performance d egradation. It may also cause logic errors, degradation in switching speed and hence timing errors. In this project, we propose pattern generation algorithms that target power supply noise more accurately with less time by reducing the pattern search space. We also investigate PSN effects on path delay, crosstalk and IR-drop. As technology is shrinking, the PSN effects are becoming more prominent.