Dr. Chintan Patel specializes in VLSI design and test and has been working on projects dealing with power supply modeling, noise estimation, current measurements circuits and hardware security.

Dr. Chintan Patel specializes in VLSI design and test. Specifically, he is working on power supply modeling, noise estimation, current measurements circuits and hardware security. “Current projects focus on modeling of the chip’s power supply network and developing a framework to estimate the current being drawn from the chip’s power pads,” explains Dr. Patel, who adds that he is  accomplishing this by using dynamic circuit level simulations.

His work focuses on using the power supply modeling framework to reduce the complexity of these simulations by simulating only a portion of the chip and using those results to estimate the response of the entire chip. “Today’s complex devices operating at very low power supply voltages are very susceptible to even minor variations in the chip’s power supply,” explains Dr. Patel, adding that modeling these variations is crucial during the chip’s design phase in order to devise ways to compensate for these variations during normal operation.

The techniques that Dr. Patel is developing can be used to estimate the average and peak power consumption of devices, to analyze the power supply network, and to predict the power supply noise at various locations on the power grid. “This work will enable us to accurately predict the power supply noise in the chip which in turn can be used to predict the effects of this noise during both functional and test mode,” explains Dr. Patel.

One of Dr. Patel’s research projects deals with predicting the increase in delay on critical paths during functional mode, as well as during delay and transition testing due to the noise generated by simultaneous switching paths. The information gathered is then used with automatic test generation tools to generate power supply noise aware test patterns which can significantly reduce overkill during transition and delay testing. “These tests can be used to analyze the power grid design, as well as ensure reliable operation by providing robustness to supply noise for critical paths,” explains Dr. Patel.

Another of Dr. Patel’s research projects lies within the hardware security domain that focuses on side-channel attack analysis and prevention as well as on detecting malicious circuits that are inserted into the chip during fabrication. The project also aims to develop new circuits and architectures for physically un-clonable functions (PUFs). In terms of his research in the hardware security domain, Dr. Patel explains that it is important to analyze information leakage through side-channels in order to prevent attacks that use this information to compromise private data. “My research focuses on estimating the amount of information being leaked by such side-channels and coming up with countermeasure solutions for preventing such attacks,” he says.