[CMSC 411 Home] | [Syllabus] | [Project] | [VHDL resource] | [Homework 1-6] | [Homework 7-12] [Files] |
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Do exercises 6.1, 6.2, 6.3 and 6.4 in textbook, pages 529-530 Read problem carefully: e.g. in 6.1 the ALU time of both the single-cycle and pipeline machines increase from 2ns to 4ns. Carefully redraw Figure 6.3 and turn this in as part of your homework.
Do exercises 6.15 and 6.16 in textbook, pages 532, 533
Do exercises 7.7 and 7.8 in textbook, page 628 with data given here: 1, 4, 2, 7, 23, 6, 17, 3, 5, 24, 40, 19, 56, 0, 18, 3
Do exercise 7.11 in textbook, Page 629. Use one clock cycle to send address and use method defined in the middle of page 560. Be careful! The cache block size is 16 words (not 4 words) thus one address causes 16 words to come into the cache. The memory cycles every 10 clocks. After the 10th clock the data goes on the bus on the next cycle. The first word comes out of the interleaved memory in 10 clocks after receiving the address. The second, third and fourth on 11, 12 and 13 respectively. Then the fifth word comes out of the first memory 20 clocks after address was received, each memories cycling overlaps the others. The wide memory lets 4 words come out each 10 clocks. Don't forget to add bus clock cycles. The cache can not indicate a hit until the 16th word comes off the bus. Show your work to get partial credit, e.g. clock cycle each word is in the cache, the total clock cycles (which is the clock cycle when the last word is in the cache), which is the miss penalty. The miss penalty would be divided by 16 to get the average increase in CPI for a cache miss. Then, hopefully the cache miss rate is low. Why can't we let the CPU execute an instruction when the first word is in the cache? Well, it might be the third word in the block that the CPU needs. OK, why can't we let the CPU execute an instruction when the word it needs is in the cache? Well, what if the CPU instruction used that word from the cache and computed a result that went into the last word in the cache block! The CPU would take 5 clocks to compute the value and put it into the cache but the cache may take 10 to 20 clocks before the last word is fetched from memory and put into the last word of the cache block, over-writing the computed value. So, the CPU pipeline is stalled while the cache is doing its job. This applies to part 3 of the project.
Be sure you understand Fig 7.24 p591 and Fig 7.25 p593
Give the total size in bits. It may not be an even number of bytes.
Clearly show how many bits are in the "virtual page number" and
in the "physical page number."
Only draw the TLB and physical address. You do not have enough
information to draw the cache in Fig 7.25
Part1: Do exercise 7.32 and 7.33 in textbook, page 632.
Part2: repeat 7.32 and 7.33 with the following data:
Assume the same 4 bits for valid, ...
Virtual address is 38 bits,
Physical address is 36 bits,
64-KB page size (16 bit page offset)
Part1: Do exercise 8.11 in textbook on page 702.
Follow the example on page 665-666 using an optimistic
memory model. The next memory access starts immediately
after the previous memory access completes.
You must do both the 4-word block transfer and the
16-word block transfer. Both cases move a total of
256 words. A word is 32 bits.
Part2: repeat 8.11 with the following data:
16 clocks to read the first four words and 6 clocks
to read each additional four words.
Read the example carefully! Bus transfers overlap the
memory access. The next memory access starts immediately
after the previous memory access completes. A time-line
diagram may be better than a formula for this problem.
Reading assignments:
Sections 2.7, 4.4, 4.5, 4.6, 4.7, 4.8,
7.3, 7.4, 7.5, 8.4, 8.6, 9.2
Homework assignments 2, 4 through 12
Project: part1 and part2
General VHDL questions.
Last updated 10/22/03