Computer Science and Electrical Engineering
Ph.D. Dissertation Proposal
Framework for Accurate Estimation of Dynamic
Power Supply Noise and its Effect on Path Delays
Sushmita K. Rao
11:00am-1:00pm Monday, July 29, 2013, ITE 346
Power-supply noise is a major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent over-stimulation during test cycle and avoid false failures.
Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Current research concentrate on static IR-drop which accounts for only part of the total voltage drop on the power grid and therefore insufficient for nanometer designs. To our knowledge, inductive drop is not included in current noise analysis techniques for simplification. The power delivery networks in today’s very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi/dt drop than resistive drop essentiating the need to be accounted. Simultaneous switching in localized areas in a chip too result in large instantaneous current to be drawn from a particular power bump or pad reducing supply voltage further. Thus, there arises a growing need to accurately characterize the resistive and inductive voltage drop caused by simultaneous switching of multiple paths. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. It is critical to account for this increase in delay during the ATPG process else it can lead to overkill during transition and delay testing. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the large number of ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test.
A scalable current-based dynamic method is presented to estimate both IR and Ldi/dt drop caused by simultaneous switching activity. Also presented is a technique to predict the increase in path delays caused by supply noise. The noise and delay estimation techniques use simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of the convolution-based techniques.
Committee: Professors Chintan Patel (Chair), Mohamed Younis, Ryan Robucci and Nilanjan Banerjee