University of Maryland Baltimore County

Department of Computer Science and Electrical Engineering

CMSC 611, Fall 2019

Advanced Computer Architecture

Tuesday and Thursday 11:30 AM - 12:45 PM, FA 215


Course Information

 Instructor and TA Contact Information

 Course Syllabus

 Grade structure and policy

 Lecture notes




Course Instructor

Dr. Mohamed Younis

Office: ITE 318



Research Lab. Embedded Systems and Networks (ESNet)

Office hours: Tuesday and Thursday 1:00 PM - 2:00 PM

Research interest:

Sensor Networks, Wireless Communications, Fault tolerant computing, Information Security, Real-time systems

Teaching assistant

TA: Yao Yao

Office: ITE 344


Office hours: Manday and Wednesday 3:30 - 4:30 PM


Grader: Adegoke Adekeye

Office: ITE 3??


Office hours: Tuesday 1:00 - 2:00 PM (only for grading related questions)


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Course Syllabus


Computer Architecture: A Quantitative Approach, 5th or 6th Edition

Computer Architecture: A Quantitative Approach, 5th or 6th Edition

John L. Hennessy and David A. Patterson

Morgan Kaufmann Publishers, ISBN 978-0-12-383872-8

Course Outline

1. Quantitative Principles of Computer Design

         The Task of a Computer Designer

         Technology and Computer Usage Trends

         Cost and Trends in Cost

         Measuring and Reporting Performance

         Benchmarks and metrics

2. Instruction Set Principles and Examples

         Classification of Instruction Set Architectures

         Instruction Formats and Semantics

         Memory Addressing Modes

         Operations in the Instruction Set

         Encoding and Instruction Set

         The Role of Compilers

3. Advanced Pipelining and Instruction-Level Parallelism

         Basic Pipeline Operations

         Data and Control Pipeline Hazards

         Instruction-Level Parallelism

         Dynamic Instruction Scheduling and Branch Prediction

4. Memory-Hierarchy Design

         Cache Design Issues

         Performance Evaluation

         Virtual Memory Addressing

         Memory Protection Mechanisms

         Memory coherency techniques

5. Storage Systems

         Types of Storage Devices

         Buses-Connecting I/O Devices to CPU/Memory

         I/O Performance Measures

         Reliability, Availability, and RAID

         Interfacing to an Operating System

6. Thread Level Parallelism

         Multiprocessor Systems and Applications

         Centralized Shared-Memory Architectures

         Distributed Shared-Memory Architectures

         Execution Synchronization

         Models of Memory Consistency

7. Data Level Parallelism (Time Permitting)

         Vector Processing

         Support for Multimedia Applications

         Graphics Processing Units

8. Warehouse-Scale Computers (Time Permitting)

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Grade Structure and Policy

Course work

Grade distribution

Midterm exam


Final exam






         Four assignments will be given and their average is to be normalized to %20 of the final grade

         Assignments are due in class. Late assignments are not accepted.

         The project is mainly hardware design assignments by writing an architecture simulator in a high level programming language, e.g., C.

         UMBC rules apply to cheating/copying. You may work together and discuss homework and the project. You must do your own work and not copy from anyone else.

         Copying/cheating will result in a minimum punishment of a zero grade for the assignment or project.

Course grade



90% - 100%


80% -89.9%


70% -79.9%


60% - 69.9%

Academic Integrity Statement:

By enrolling is this course, each student assumes the responsibilities of an active participant in UMBC's scholarly community in which everyone's academic work and behavior and held to the highest standards of honesty. Cheating, fabrication, plagiarism, and helping others to commit these acts are all forms of academic dishonesty, and they are wrong. Academic misconduct could result in disciplinary action that may include, but is not limited to, suspension or dismissal. To find useful information about avoiding plagiarism infractions through appropriate citations, or to read the full policy regarding student academic misconduct for the graduate school, please see

Title IX/Sexual Misconduct Statement:

Any student who has experienced sexual harassment or assault, relationship violence, and/or stalking is encouraged to seek support and resources. There are a number of resources available to you. With that said, as an instructor, I am considered a Responsible Employee, per UMBC'S interim Policy on Prohibited Sexual Misconduct, Interpersonal Violence, and Other Related Misconduct. This means that while I am here to listen and support you, I am required to report disclosures of sexual assault, domestic violence, relationship violence, stalking, and/or gender-based harassment to the University's Title IX Coordinator. The purpose of these requirements is for the University to inform you of options, supports, and resources. You can utilize support and resources even if you do not want to take any further action. You will not be forced to file a police report, but please be aware, depending on the nature of the offense, the University may take action.

If you need to speak with someone in confidence about an incident, UMBC has the following Confidential Resources available to support you:
- The Counseling Center: 410-455-2742 (M-F 8:30-5:00)
- University Health Services: 410-455-2542 (M-F 8:30-5:00)
- For after-hours emergency consultation, call the police at 410-455-5555

Other on-campus supports and resources:
- The Women's Center (available to students of all genders): 410-455-2714 (M-Th 9:306, F 9:30-4:00)
- Title IX Coordinator: 410-455-1606 (9:00-5:00)

Child Abuse and Neglect:
Please note that Maryland law requires that I report all disclosures or suspicions of child abuse or neglect to the Department of Social Service and/or the police. /span>.

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Lecture notes





August 29, 2019

  Introduction and overview


September 3, 2019

  Cost and Performance of Computers


September 5, 2019

  Performance Summary and Benchmarks


September 10, 2019

  Instruction Set Architecture (I)


September 12, 2019

  Instruction Set Architecture (II)


September 17, 2019

  Introduction to Pipelining


September 19, 2019

  Pipeline Hazards


September 24, 2019

  Control Hazards and Exception Handling


September 26, 2019

  Pipeline Implementation Challenges


October 1, 2019

  Instruction Level Parallelism


October 3, 2019

  Dynamic Pipeline Scheduling


October 8, 2019

  Dynamic Branch Prediction


October 10, 2019

  Tomasulo's Dynamic Instruction Scheduling Algorithm


October 15, 2019

  ILP with Multiple Instruction Issue


October 17, 2017



October 22, 2019

  Midterm exam


October 24, 2019

  Hardware Assisted Speculative Execution


October 29, 2019

  Memory Hierarchy and Basics of Cache


October 31, 2019

  Reducing Cache Miss Rate


November 5, 2019

  Optimizing Cache Performance


November 7, 2019

  Main Memory


November 12, 2019

  I/O Systems


November 14, 2019

  Performance and Interfacing I/O Devices


November 19, 2019

  Introduction to Multiprocessor Systems


November 21, 2019

  Vector Processing (time permitting)


November 26, 2019

  Multimedia SIMD and Graphic Processing Units (time permitting)


December 3, 2019

  Cache Coherence Protocols


December 5, 2019

  Warehouse-Scale Computers (time permitting)


December 10, 2019



December 12, 2019

 Final exam (10:30 AM-12:30 PM)

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Date Out

Due Date

Assignment #1

 September 12, 2019

September 19, 2019

Assignment #2

 September 26, 2019

October 3, 2017

Assignment #3

 October 10, 2019

October 17, 2019

Assignment #4

 November 14, 2019

November 21, 2019

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Date Out

Due Date

Term Project

October 10, 2019

December 3, 2019

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  Cadance VHDL Resources

  Cadance VHDL Tutorial (Jim Plusquellic)

  VHDL Tutorial slides (Jim Plusquellic)

  VHDL References (Jon Squire)

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Last Revised: November 4, 2019