University of Maryland Baltimore County

Department of Computer Science and Electrical Engineering

CMSC 611, Fall 2020

Advanced Computer Architecture

Tuesday and Thursday 11:30 AM - 12:45 PM, Online


Course Information

 Instructor and TA Contact Information

 Course Syllabus

 Grade structure and policy

 Lecture notes



Course Instructor

Dr. Mohamed Younis

Office: ITE 318



Research Lab. Embedded Systems and Networks (ESNet)

Office hours: Tuesday and Thursday 1:00 PM - 2:00 PM

Research interest:

Sensor Networks, Wireless Communications, Fault tolerant computing, Information Security, Real-time systems

Teaching assistant

TA: Yao Yao

Office: ITE 344


Office hours: Monday and Wednesday 3:30 - 4:30 PM


Back to top

Course Syllabus


Computer Architecture: A Quantitative Approach, 5th or 6th Edition

Computer Architecture: A Quantitative Approach, 5th or 6th Edition

John L. Hennessy and David A. Patterson

Morgan Kaufmann Publishers, ISBN 978-0-12-383872-8

Course Outline

1. Quantitative Principles of Computer Design

         The Task of a Computer Designer

         Technology and Computer Usage Trends

         Cost and Trends in Cost

         Measuring and Reporting Performance

         Benchmarks and metrics

2. Instruction Set Principles and Examples

         Classification of Instruction Set Architectures

         Instruction Formats and Semantics

         Memory Addressing Modes

         Operations in the Instruction Set

         Encoding and Instruction Set

         The Role of Compilers

3. Advanced Pipelining and Instruction-Level Parallelism

         Basic Pipeline Operations

         Data and Control Pipeline Hazards

         Instruction-Level Parallelism

         Dynamic Instruction Scheduling and Branch Prediction

4. Memory-Hierarchy Design

         Cache Design Issues

         Performance Evaluation

         Virtual Memory Addressing

         Memory Protection Mechanisms

         Memory coherency techniques

5. Storage Systems

         Types of Storage Devices

         Buses-Connecting I/O Devices to CPU/Memory

         I/O Performance Measures

         Reliability, Availability, and RAID

         Interfacing to an Operating System

6. Thread Level Parallelism

         Multiprocessor Systems and Applications

         Centralized Shared-Memory Architectures

         Distributed Shared-Memory Architectures

         Execution Synchronization

         Models of Memory Consistency

7. Data Level Parallelism (Time Permitting)

         Vector Processing

         Support for Multimedia Applications

         Graphics Processing Units

8. Warehouse-Scale Computers (Time Permitting)

Back to top

Grade Structure and Policy

Course work

Grade distribution

Midterm exam


Final exam






         Four assignments will be given and their average is to be normalized to %20 of the final grade

         Assignments are due in class. Late assignments are not accepted.

         The project is mainly hardware design assignments by writing an architecture simulator in a high level programming language, e.g., C.

         UMBC rules apply to cheating/copying. You may work together and discuss homework and the project. You must do your own work and not copy from anyone else.

         Copying/cheating will result in a minimum punishment of a zero grade for the assignment or project.

Course grade



90% - 100%


80% -89.9%


70% -79.9%


60% - 69.9%

Academic Integrity Statement:

By enrolling is this course, each student assumes the responsibilities of an active participant in UMBC's scholarly community in which everyone's academic work and behavior and held to the highest standards of honesty. Cheating, fabrication, plagiarism, and helping others to commit these acts are all forms of academic dishonesty, and they are wrong. Academic misconduct could result in disciplinary action that may include, but is not limited to, suspension or dismissal. To find useful information about avoiding plagiarism infractions through appropriate citations, or to read the full policy regarding student academic misconduct for the graduate school, please see

Title IX/Sexual Misconduct Statement:

Any student who has experienced sexual harassment or assault, relationship violence, and/or stalking is encouraged to seek support and resources. There are a number of resources available to you. With that said, as an instructor, I am considered a Responsible Employee, per UMBC'S interim Policy on Prohibited Sexual Misconduct, Interpersonal Violence, and Other Related Misconduct. This means that while I am here to listen and support you, I am required to report disclosures of sexual assault, domestic violence, relationship violence, stalking, and/or gender-based harassment to the University's Title IX Coordinator. The purpose of these requirements is for the University to inform you of options, supports, and resources. You can utilize support and resources even if you do not want to take any further action. You will not be forced to file a police report, but please be aware, depending on the nature of the offense, the University may take action.

If you need to speak with someone in confidence about an incident, UMBC has the following Confidential Resources available to support you:
- The Counseling Center: 410-455-2742 (M-F 8:30-5:00)
- University Health Services: 410-455-2542 (M-F 8:30-5:00)
- For after-hours emergency consultation, call the police at 410-455-5555

Other on-campus supports and resources:
- The Women's Center (available to students of all genders): 410-455-2714 (M-Th 9:306, F 9:30-4:00)
- Title IX Coordinator: 410-455-1606 (9:00-5:00)

Child Abuse and Neglect:
Please note that Maryland law requires that I report all disclosures or suspicions of child abuse or neglect to the Department of Social Service and/or the police. /span>.

Back to top              

Lecture notes





August 27, 2020

  Introduction and overview


September 1, 2020

  Cost and Performance of Computers


September 3, 2020

  Performance Summary and Benchmarks


September 8, 2020

  Instruction Set Architecture (I)


September 10, 2020

  Instruction Set Architecture (II)


September 15, 2020

  Introduction to Pipelining


September 17, 2020

  Pipeline Hazards


September 22, 2020

  Control Hazards and Exception Handling


September 24, 2020

  Pipeline Implementation Challenges


September 29, 2020

  Instruction Level Parallelism


October 1, 2020

  Dynamic Pipeline Scheduling


October 6, 2020

  Dynamic Branch Prediction


October 8, 2020

  Tomasulo's Dynamic Instruction Scheduling Algorithm


October 13, 2020

  ILP with Multiple Instruction Issue


October 15, 2017



October 20, 2020

  Midterm exam


October 22, 2020

  Hardware Assisted Speculative Execution


October 27, 2020

  Memory Hierarchy and Basics of Cache


October 29, 2020

  Reducing Cache Miss Rate


October 31, 2020

  Optimizing Cache Performance


November 5, 2020

  Main Memory


November 10, 2020

  I/O Systems


November 12, 2020

  Performance and Interfacing I/O Devices


November 17, 2020

  Introduction to Multiprocessor Systems


November 19, 2020

  Vector Processing (time permitting)


November 24, 2020

  Multimedia SIMD and Graphic Processing Units (time permitting)


December 1, 2020

  Cache Coherence Protocols


December 3, 2020

  Warehouse-Scale Computers (time permitting)


December 8, 2020



December 10, 2020

 Final exam (10:30 AM-12:30 PM)

Back to top



Date Out

Due Date

Assignment #1

 September 10, 2020

September 17, 2020

Assignment #2

 September 24, 2020

October 1, 2017

Assignment #3

 October 8, 2020

October 15, 2020

Assignment #4

 November 17, 2020

November 24, 2020

Back to top



Date Out

Due Date

Term Project

October 8, 2020

December 1, 2020

Back to top

Last Revised: August 11, 2020