University of
Department of Computer Science and Electrical
Engineering
CMSC 611-101, Fall 2007
Advanced Computer Architecture
Tuesday and Thursday 10:00 AM -
11:15 AM ITE 233
Course
Information
Instructor and TA Contact
Information
Dr. Mohamed Younis
Office: ITE 318
E-mail: younis@cs.umbc.edu
URL: http://www.cs.umbc.edu/~younis
Office hours: Tuesday and Thursday 11:15 AM - 12:15
PM
Research interest:
Wireless Networks, Real-time systems, Fault tolerant
computing, Tool support for embedded systems, Network Security
Teaching assistant
Mr. Sourav Mukherjee
Office: ITE 349
E-mail: sourav1@umbc.edu
Office hours: Monday and
Wednesday 10:00 AM - 12:00 PM
Textbook:
Computer Architecture: A Quantitative Approach, Third Edition
John L. Hennessy and David A. Patterson
Morgan Kaufmann Publishers, ISBN 1-55860-596-7
Course
Outline
1. Quantitative Principles of Computer Design
· The Task of a Computer Designer
· Technology and Computer Usage Trends
· Cost and Trends in Cost
· Measuring and Reporting Performance
· Benchmarks and metrics
· Classification of Instruction Set Architectures
·
Instruction
Formats and Semantics
·
Memory
Addressing Modes
·
Operations in
the Instruction Set
·
Encoding and Instruction
Set
·
The Role of
Compilers
·
Basic Pipeline
Operations
·
Data and Control
Pipeline Hazards
·
Instruction-Level
Parallelism
·
Dynamic
Instruction Scheduling and Branch Prediction
·
Cache Design
Issues
·
Performance
Evaluation
·
Virtual Memory
Addressing
·
Memory
Protection Mechanisms
·
Memory coherency
techniques
·
Types of Storage
Devices
·
Buses-Connecting
I/O Devices to CPU/Memory
·
I/O Performance
Measures
·
Reliability,
Availability, and RAID
·
Interfacing to
an Operating System
·
Interconnection
network Media
·
Connecting More
Than Two Computers
·
Practical Issues
for Commercial Interconnection Networks
·
Examples of
Interconnection Networks
7. Multiprocessors (Time Permitting)
·
Characteristics
of Application Domains
·
Centralized
Shared-Memory Architectures
·
Distributed
Shared-Memory Architectures
·
Execution
Synchronization
·
Models
of Memory Consistency
Course work
Grade distribution
Midterm exam
30%
Final exam
30%
Project
25%
Homework
15%
· 3 assignments will be given and their average is to be normalized to %15 of the final grade
· Assignments are due in class. Late assignments are not accepted.
· The scope of the exams is incremental (final exam is not comprehensive)
· The project is mainly hardware design assignments by writing an architecture simulator in a high level programming language, e.g., C.
· UMBC rules apply to cheating/copying. You may work together and discuss homework and the project. You must do your own work and not copy from anyone else.
· Copying/cheating will result in a minimum punishment of a zero grade for the assignment or project.
Course grade
Range
A
90% - 100%
B
80% -89.9%
C
70% -79.9%
D
60% - 69.9%
Lecture
Date
Subject
1
August 30, 2007
2
September 4, 2007
3
September 6, 2007
4
September 11, 2007
5
September 13, 2007
6
September 18, 2007
7
September 20, 2007
8
September 25, 2007
9
September 27, 2007
10
October 2, 2007
11
October 4, 2007
12
October 9, 2007
Dynamic Pipeline Scheduling (Cont.)
13
October 11, 2007
14
October 16, 2007
15
October 18, 2007
16
October 23, 2007
Midterm exam #1
17
October 25, 2007
Hardware Assisted Speculative Execution
18
October 30, 2007
19
November 1, 2007
20
November 6, 2007
21
November 8, 2007
Optimizing Cache Performance (Cont.)
22
November 13, 2007
23
November 15, 2007
Main Memory (Cont.)
24
November 20, 2007
Main Memory (Cont.)
25
November 27, 2007
26
November 29, 2007
27
December 4, 2007
28
December 6, 2007
Introduction to Multiprocessor Systems
29
December 11, 2007
Cache Coherence Protocols
30
December 18, 2007
Final exam (10:30 AM-12:30 PM)
Assignment
Date Out
Due Date
September 13, 2007
September 20, 2007
October 9, 2007
October 16, 2007
November 20, 2007
November 27, 2007
|
Project |
Date Out |
Due Date |
|
October 18, 2007 |
November 29, 2007 |
§ Cadance VHDL Tutorial (Jim Plusquellic)
Last Revised: November 20th, 2007