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library IEEE; use IEEE.std_logic_1164.all; entity alu_32 is -- given. Do not change this interface port(inA : in std_logic_vector (31 downto 0); inB : in std_logic_vector (31 downto 0); inst : in std_logic_vector (31 downto 0); result : out std_logic_vector (31 downto 0)); end entity alu_32; architecture schematic of alu_32 is signal cin : std_logic := '0'; signal cout : std_logic; -- add or change signals as required begin -- schematic bsh: entity WORK.bshift port map(left => sllop, logical => '1', shift => inst(10 downto 6), input => inB, output => bresult); ORR : entity WORK.equal6 port map(inst(31 downto 26), "000000", RRop); Oor: entity WORK.equal6 port map(inst(5 downto 0), "001101", orop); Omul: entity WORK.equal6 port map(inst(5 downto 0), "011011", mulop); Odiv: entity WORK.equal6 port map(inst(5 downto 0), "011000", divop); -- ??? insert other xxxop statements from cs411_opcodes.txt orop_and <=orop and RRop; mulop_and <=mulop and RRop; divop_and <=divop and RRop; -- ??? insert other xxx_and statements adder: entity WORK.add32 port map(a => inA, b => inB, cin => cin, sum => aresult, cout => cout); Mul: entity WORK.pmul8 port map(inA(7 downto 0), inB(7 downto 0), mulresult(15 downto 0)); Div: entity WORK.divcas16 port map(inA(31 downto 0), inB(15 downto 0), divquo(15 downto 0), divrem(15 downto 0)); divquo32 <= z16&divquo; divrem32 <= z16&divrem; -- not used yet Omux: entity WORK.mux32_6 port map(in0=>aresult, in1=>bresult, in2=>andresult, in3=>orresult, in4=>mulresult, in5=>divquo32, ct1=>S_sel, ct2=>andop_and, ct3=>orop_and, ct4=>mulop_and, ct5=>divop_and, result=>result); end architecture schematic; -- of alu_32