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CS411 ALU for project Part1

  


library IEEE;
use IEEE.std_logic_1164.all;

entity alu_32 is -- given. Do not change this interface
  port(inA    : in  std_logic_vector (31 downto 0);
       inB    : in  std_logic_vector (31 downto 0);
       inst   : in  std_logic_vector (31 downto 0);
       result : out std_logic_vector (31 downto 0));
end entity alu_32;


architecture schematic of alu_32 is 
  signal cin     : std_logic := '0';
  signal cout    : std_logic;

  -- add or change  signals as required 

begin  -- schematic
  adder: entity WORK.add32 port map(a    => inA,
                                    b    => inB,    -- change
                                    cin  => cin,    -- change
                                    sum  => result, -- change
                                    cout => cout);

  -- bsh: entity WORK.bshift port map(left => sllop,
  --                                  logical => '1',
  --                                  shift => inst(10 downto 6),
  --                                  input => inB,
  --                                  output => bresult);

  -- r1: entity WORK.equal6 port map(inst => inst(31 downto 26),
  --                                 test => "000000",
  --                                 equal => rrop);

  -- ...
  -- a1: subop <= rrop and ????;
  -- ...

end architecture schematic;  -- of alu_32