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CMSC 411 Computer Architecture Syllabus Spring 2009

Class schedule, topic and assignments for both sections

 0101 Tuesday and Thursday   11:30pm-12:45pm  ITE 229
 0201 Tuesday and Thursday    5:30pm- 6:45pm  SOND 110

 Reading assignments: from third edition of textbook, 4th ed OK.
 Homework and projects are due on the later date listed.
 Computer Engineering majors have additional tasks in
 some assignments.


Lec Date   Subject                                 Reading     Homework
                                                               assigned due

 1.
    1/27   Introduction, terminology               1.1-1.5     HW1

 2. 
    1/29   Benchmarks                              4.1-4.5

 3. 
    2/3    Performance,                            4.4-4.7     HW2       HW1

 4. 
    2/5    CPU operation                      skim 2.1-2.7
                                              read p60-64  

 5. 
    2/10   Instructions and registers         skim 2.8-2.15    HW3       HW2
                                              read p97-101

 6. 
    2/12   VHDL introduction                  VHDL WEB Pages

 7. 
    2/17   Arithmetic                              3.1-3.3     HW4       HW3
                                              VHDL WEB Pages

 8. 
    2/19   ALU                                B.5-B.6 on CD          

 9. 
    2/24   Multiply                                3.4         HW5

 10. 
    2/26   Divide                                  3.5                   HW4*

 11. 
    3/3    Floating Point                          3.6 

 12. 
    3/5    VHDL - circuits and debugging     VHDL web pages    HW6       HW5

 13. 
    3/10   Microprogramming - review               5.5

 14. 
    3/12   mid-term exam                                       study

Spring Break 3/16 - 3/22

 15. 
    3/24   Control Unit                            5.1-5.4               HW6*

 16. 
    3/26   Pipelining 1                            6.1    

 17. 
    3/31   Pipelining 2                            6.2-6.3     HW7

 18. 
    4/2    Project outline and VHDL          VHDL web pages    proj1

 19. 
    4/7    Pipelining Data Forwarding              6.4-6.6     proj2a    HW7

 20. 
    4/9    Hazard and stalls                       6.4-6.6     HW8       Proj1*
                                                               proj2b

 21. 
    4/14   Cache                                   7.1-7.2     HW9

 22. 
    4/16   Cache performance                       7.3         proj3a

 23. 
    4/21   Virtual memory 1                        7.4-7.5     HW10      HW8     
                                                                         Proj2a*

 24. 
    4/23   Virtual memory 2                        WEB page    proj3b    HW9

 25. 
    4/28   I/O types and performance               8.1-8.3     HW11      HW10
                                                                         Proj2b*

 26. 
    4/30   DVR, DVD-RW, CDR, CD-RW                 WEB page

 27.
    5/5    Busses, I/O-processor connection        8.4-8.7     HW12      HW11
                                                                         Proj3a*

 28. 
    5/7    Multiprocessors                    skim 9.1-9.4

 29. 
    5/12   Review                                              study     HW12
                                                                         Proj3b*

 30. 
  5/14  Final Exam 0101  10:30am-12:30pm  room ITE 229  (none other than these two)
  5/14  Final Exam 0201  6:00pm-8:00pm   room SOND 110  (none other than these two)
  (take either exam, Bring ID card, show when turning in exam.)

    No late homework or project accepted after midnight 5/14
    Late penalty is 10% per week, penalty limit 50%.
    * submitted, not graded until next weekend (not late for a while)
    Projects are graded only once, do not do "submit" until finished.
    Check will be made for copying after midnight 5/14.
    Missing or copied projects get a zero.

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Last updated 4/16/09