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Project part1 starts with part1_start.vhdl
Search for "???" where you need to do some work.
The schematic is:
with ALU schematic
Extracted code to indicate where you need to do some work "...":
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_32 is -- given. Do not change this interface
port(inA : in std_logic_vector (31 downto 0);
inB : in std_logic_vector (31 downto 0);
inst : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0));
end entity alu_32;
architecture schematic of alu_32 is
signal cin : std_logic := '0';
signal cout : std_logic;
-- ... add or change signals as required
begin -- schematic
adder: entity WORK.add32 port map(a => inA,
b => inB, -- ... change
cin => cin, -- ... change
sum => result, -- ... change
cout => cout);
-- ...
-- bsh: entity WORK.bshift port map(left => sllop,
-- logical => '1',
-- shift => inst(10 downto 6),
-- input => inB,
-- output => bresult);
-- ...
-- r1: entity WORK.equal6 port map(inst => inst(31 downto 26),
-- test => "000000",
-- equal => rrop);
-- ...
-- a1: subop <= rrop and ????;
-- ...
end architecture schematic; -- of alu_32
The additional files needed are:
part1.abs the program to be executed
part1.run to stop execution, no halt instruction
part1.chk the expected output
cs411_opcodes.txt opcode bit patterns
Modify your Makefile :
all: ... part1.out
part1.out: add32.vhdl bshift.vhdl part1.vhdl part1.abs part1.run
ncvhdl -v93 add32.vhdl
ncvhdl -v93 bshift.vhdl
ncvhdl -v93 part1.vhdl # renamed and modified part1_start.vhdl
ncelab -v93 part1:schematic
ncsim -batch -logfile part1.out -input part1.run part1
optional in Makefile, should be run on GL before submit cs411 part1 part1.vhdl
diff -iw part1.out part1.chk should be no differences other
than copyright or dates
The project writeup:
cs411_proj.shtml
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