The most important item on all homework is YOUR NAME! No name, no credit. ALSO, put last 4 digits of your SS#. Staple or clip pages together.
Homework must be submitted when due. You loose 10%, one grade, the first day homework is late. Then 10% each week there after. Max 50% off. A zero really hurts your average. Paper or EMail to squire@cs.umbc.edu is acceptable. If I can not read or understand your homework, you do not get credit. Type or print if your handwriting is bad. Homework is always due on a scheduled class day within 15 minutes after the start of the class. If class is canceled then homework is due the next time the class meets.
EMail only plain text! No word processor formats.
You may use a word processor or other software tools and
print the results and turn in paper.
Try using ^R in Pine, ~r in BSD Mail.
Do exercises 6.1, 6.2, 6.3 and 6.4 in textbook, pages 529-530 Read problem carefully: e.g. in 6.1 the ALU time of both the single-cycle and pipeline machines increase from 2ns to 4ns. Carefully redraw Figure 6.3 and turn this in as part of your homework. Show work for all problems.
Do exercises 6.15 and 6.16 in textbook, pages 532, 533
Do exercises 7.7 and 7.8 in textbook, page 628.
Do exercises 7.32 and 7.33 in textbook, page 632.
Do exercise 7.11 in textbook, Page 629. Use one clock cycle to send address and use method defined in the middle of page 560. Be careful! The cache block size is 16 words (not 4 words) thus one address causes 16 words to come into the cache. The first word comes out of the interleaved memory in 10 clocks. The second, third and fourth on clock 11, 12 and 13 respectively. But, then the fifth word comes out on clock 20, etc. The wide memory lets 4 words come out each 10 clocks. Bus transfer time does not increase the total time to get 16 words into the cache except on the last transfer. Show your work to get partial credit, e.g. clock cycle each word is in the cache, the total clock cycles (which is the clock cycle when the last word is in the cache), which is the miss penalty. This may look bad saying it this way, but the miss penalty would be divided by 16 to get the average increase in CPI for a cache miss. Then, hopefully the cache miss rate is low. Why can't we let the CPU execute an instruction when the first word is in the cache? Well, it might be the third word in the block that we need. OK, why can't we let the CPU execute an instruction when the word it needs is in the cache? Well, what if the CPU instruction used that word from the cache and computed a result that went into the last word in the cache block! The CPU would take 5 clocks to compute the value and put it into the cache but the cache may take 10 to 20 clocks before the last word is fetched from memory and put into the last word of the cache block, over writing the computed value. So, the CPU pipeline is stalled while the cache is doing its job. This applies to part 3 of the project.
Do exercise 8.11 in textbook on page 702
Reading assignments:
Sections 2.7, 4.4, 4.5, 4.6, 4.7, 4.8,
7.3, 7.4, 7.5, 8.4, 8.6, 9.2
Homework assignments 2, 4 through 12
Project: part1 and part2
General esim questions.
Last updated 12/14/99