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CMSC 411 Computer Architecture Syllabus Fall 2006

Class schedule, topic and assignments for both sections

 0101 Tuesday and Thursday   4:00-5:15  BIOL 120
 0201 Wednesday and Friday   2:30-3:45  Physics, LH 6

 Reading assignments: from third edition of textbook.
 The same handout and lecture is given on two days.
 Homework and projects are due on the later date.
 Computer Engineering majors have additional tasks.


Lec Date   Subject                                 Reading     Homework
                                                               assigned due

 1.
    8/30  Introduction, terminology                1.1-1.5     HW1
    8/31

 2. 
    9/1    Benchmarks                              4.1-4.5
    9/5 

 3. 
    9/6    Performance,                            4.4-4.7     HW2       HW1
    9/7

 4. 
    9/8    CPU operation                      skim 2.1-2.7
    9/12                                      read p60-64  

 5. 
    9/13   Instructions and registers         skim 2.8-2.15    HW3       HW2
    9/14                                      read p97-101

 6. 
    9/15   VHDL introduction                 VHDL WEB Pages
    9/19   (optional if you know VHDL)

 7. 
    9/20   Arithmetic                              3.1-3.3     HW4       HW3
    9/21                                     VHDL WEB Pages

 8. 
    9/22   ALU                               B.5-B.6 on CD
    9/26                                       

 9. 
    9/27   Multiply                                3.4         HW5
    9/28

 10. 
    9/29   Divide                                  3.5                   HW4*
    10/3

 11. 
    10/4   Floating Point                          3.6 
    10/5

 12. 
    10/6   VHDL - circuits and debugging     VHDL web pages    HW6       HW5
    10/10

 13. 
    10/11 Microprogramming - review                5.5
    10/12

 14. 
    10/13 mid-term exam                            study
    10/17

 15. 
    10/18 Control Unit                             5.1-5.4
    10/19

 16. 
    10/20 Pipelining 1                             6.1                   HW6*
    10/24

 17. 
    10/25 Pipelining 2                             6.2-6.3 
    10/26

 18. 
    10/27 Project outline and VHDL          VHDL web pages     HW7
    10/31                                                      PROJ

 19. 
    11/1  Pipelining Data Forwarding               6.4-6.6     
    11/2

 20. 
    11/3  Hazard and stalls                        6.4-6.6     HW8
    11/7

 21. 
    11/8  Cache                                    7.1-7.2     HW9       HW7
    11/9                                                            Proj 1*

 22. 
    11/10 Cache performance                        7.3                   HW8
    11/14

 23. 
    11/15 Virtual memory 1                         7.4-7.5     HW10      HW9     
    11/16                                                            Proj 2a*

 24. 
    11/17 Virtual memory 2                         WEB page
    11/21

 25. 
    11/22 I/O types and performance                8.1-8.3     HW11     HW10
    11/28

 26. 
    11/29 DVR, DVD-RW, CDR, CD-RW                  WEB page
    11/30                                                            Proj 2b*

 27. 
    12/1  Busses, I/O-processor connection         8.4-8.7     HW12     HW11
    12/5

 28. 
    12/6  Multiprocessors                     skim 9.1-9.4           Proj 3a*
    12/7

 29. 
    12/8  Review                                   study                HW12
    12/12                                                            Proj 3b*

 30. 
    12/18  Final Exam 0201 1:00-3:00 LH6->LH4    (none other than these two)
    Moved to Lecture Hall 4 due to room conflict !!!!


    12/19  Final Exam 0101 3:30-5:30 BIOL 120 (none other than these two)

    No late homework or project accepted after midnight 12/19
    Late penalty is 10% per week, penalty limit 50%.
    * submitted, not graded until next weekend (not late for a while)

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Last updated 12/17/06