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CMSC 411 Computer Architecture Syllabus Fall 2005

Class schedule, topic and assignments for both sections

 0101 Tuesday and Thursday   4:00-5:15  BIOL 120
 0201 Wednesday and Friday   2:30-3:45  ACIV 305
 0301 Tuesday and Thursday   5:30-6:55  ACIV 014

 Reading assignments: from third edition of textbook.
 The same handout and lecture is given on two days.
 Homework and projects are due on the later date.
 Computer Engineering majors have additional tasks.


Lec Date   Subject                                 Reading     Homework
                                                               assigned due
 1. 8/31  Introduction, terminology                1.1-1.5     HW1
    9/1
 
 2. 9/2    Benchmarks                              4.1-4.5
    9/6 

 3. 9/7    Performance,                            4.4-4.7     HW2       HW1
    9/8

 4. 9/9    CPU operation                      skim 2.1-2.7
    9/13                                      read p60-64  

 5. 9/14   Instructions and registers         skim 2.8-2.15    HW3       HW2
    9/15                                      read p97-101

 6. 9/16   VHDL introduction                 Ashen 1.1-1.5
    9/20   (optional if you know VHDL)       VHDL web pages

 7. 9/21   Arithmetic                              3.1-3.3     HW4       HW3
    9/22                                     Ashen 8.5

 8. 9/23   ALU                                     B.5-B.6 on CD
    9/27                                       

 9. 9/28   Multiply                                3.4         HW5
    9/29                                     Ashen 6.1-6.3

10. 9/30   Divide                                  3.5                   HW4*
    10/4

11. 10/5   Floating Point                          3.6 
    10/6

12. 10/7   VHDL - circuits and debugging     VHDL web pages    HW6       HW5
    10/11                                    Ashen 18.1-18.2

13. 10/12 Microprogramming - review                5.5
    10/13

14. 10/14 mid-term exam                            study
    10/18

15. 10/19 Control Unit                             5.1-5.4
    10/20

16. 10/21 Pipelining 1                             6.1                   HW6*
    10/25

17. 10/26 Pipelining 2                             6.2-6.3 
    10/27

18. 10/28 Project outline and VHDL          VHDL web pages     HW7
    11/1                                    Ashen  5.1-5.5     PROJ

19. 11/2   Pipelining Data Forwarding              6.4-6.6     
    11/3

20. 11/4   Hazard and stalls                       6.4-6.6     HW8
    11/8

21. 11/9   Cache                                   7.1-7.2     HW9       HW7
    11/10                                                            Proj 1*

22. 11/11  Cache performance                       7.3                   HW8
    11/15

23. 11/16  Virtual memory 1                        7.4-7.5     HW10      HW9     
    11/17                                                            Proj 2a*

24. 11/18 Virtual memory 2                        handout
    11/22

25. 11/23  I/O types and performance               8.1-8.3     HW11     HW10
    11/29

26. 11/30  DVR, DVD-RW, CDR, CD-RW                 handout
    12/1                                                             Proj 2b*

27. 12/2   Busses, I/O-processor connection        8.4-8.7     HW12     HW11
    12/6

28. 12/7   Multiprocessors                    skim 9.1-9.4           Proj 3a*
    12/8

29. 12/9   Review                                  study                HW12
    12/13                                                            Proj 3b*

30. 12/15 6:00pm - 8:00pm  Final Exam 0301 ACIV 014 (none other than these three)
    12/19 1:00pm - 3:00pm  Final Exam 0201 ACIV 305 (none other than these three)
    12/20 3:30pm - 5:30pm  Final Exam 0101 BIOL 120 (none other than these three)

    No late homework or project accepted after midnight 12/20
    Late penalty is 10% per week, penalty limit 50%.
    * submitted, not graded until next weekend (not late for a while)

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Last updated 12/6/05