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CMSC 411 Computer Architecture Syllabus Fall 2004

Class schedule, topic and assignments

 Wednesday and Friday   2:00-3:15  ACIV 151
 Tuesday   and Thursday 4:00-5:15  SS 209 [same information]

 Reading assignments:
   (2) is second edition of textbook
   (3) is third  edition of textbook


Lec Date   Subject                                 Reading     Homework
                                                               assigned due
 1. 9/1   Introduction, terminology            (2) 1.1-1.6     HW1
    9/2                                        (3) 1.1-1.5

 2. 9/3    Benchmarks                          (2) 2.1-2.5
    9/7                                        (3) 4.1-4.5
 
 3. 9/8    Performance,                        (2) 2.6-2.8     HW2       HW1
    9/9                                        (3) 4.4-4.7

 4. 9/10   CPU operation                  (2) skim 3.1-3.7
    9/14                                  (2) read p117-121
                                          (3) skim 2.1-2.7
                                          (3) read p60-64  

 5. 9/15   Instructions and registers     (2) skim 3.8-3.11    HW3       HW2
    9/16                                  (2) read p145-150
                                          (3) skim 2.8-2.15
                                          (3) read p97-101

 6. 9/17   VHDL introduction                 Ashen 1.1-1.5
    9/21   (optional if you know VHDL)       VHDL web pages

 7. 9/22   Arithmetic                          (2) 4.1-4.4     HW4       HW3
    9/23                                       (3) 3.1-3.3
                                             Ashen 8.5

 8. 9/24   ALU                                 (2) 4.5
    9/28                                       (3) B.5-6 on CD

 9. 9/29   Multiply                            (2) 4.6         HW5
    9/30                                       (3) 3.4
                                             Ashen 6.1-6.3

10. 10/1   Divide                              (2) 4.7                   HW4*
    10/5                                       (3) 3.5

11. 10/6   Floating Point                      (2) 4.8 
    10/7                                       (3) 3.6

12. 10/8   VHDL - circuits and debugging     VHDL web pages    HW6       HW5
    10/12                                     Ashen 18.1-18.2

13. 10/13  Control Unit                        (2) 5.1-5.3
    10/14                                      (3) 5.1-5.4

14. 10/15  Microprogramming - review           (2) 5.4-5.5
    10/19                                      (3) 5.5

15. 10/20  mid-term exam                                       study
    10/21 

16. 10/22  Pipelining 1                        (2) 6.1                   HW6*
    10/26                                      (3) 6.1

17. 10/27  Pipelining 2                        (2) 6.2-6.3 
    10/28                                      (3) 6.2-6.3

18. 10/29  Project outline and VHDL          VHDL web pages    HW7
    11/2                                     Ashen 5.1-5.5     PROJ

19. 11/3   Pipelining Data Forwarding, Hazard  (2) 6.4-6.6     HW8
    11/4                                       (3) 6.4-6.6

20. 11/5   Cache                               (2) 7.1-7.2            Proj 1*
    11/9                                       (3) 7.1-7.2     HW9       HW7

21. 11/10  Cache performance                   (2) 7.3                   HW8
    11/11                                      (3) 7.3

22. 11/12  Virtual memory 1                    (2) 7.4-7.5     HW10      HW9     
    11/16                                      (3) 7.4-7.5           Proj 2a*

23. 11/17  Virtual memory 2                        handout
    11/18

24. 11/19  I/O types and performance           (2) 8.1-8.3     HW11      HW10
    11/23                                      (3) 8.1-8.3

25. 11/24  Open Discussion of current processors
    11/30  and operating system performance

    11/25  Thanksgiving holiday
    11/26  Thanksgiving holiday

26. 12/1  DVR, DVD-RW, CDR, CD-RW                 handout
    12/2                                                             Proj 2b*

27. 12/3   Busses, I/O-processor connection    (2) 8.4-8.6     HW12      HW11
    12/7                                       (3) 8.4-8.7

28. 12/8   Multiprocessors                (2) skim 9.1-9.4           Proj 3a*
    12/9                                  (3) skip 9.1-9.4

29. 12/10  Review                                  study                 HW12
    12/14                                                             Proj 3b*

30. 12/20 1:00pm - 3:00pm  Final Exam, Monday WF (none other than these two)
    12/16 3:30pm - 5:50pm  Final Exam, Thursday  (none other than these two)

    No late homework or project accepted after midnight 12/20
    Late penalty is 10% per week, limit 50%.
    * submitted, not graded until next weekend (not late for a while)

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Last updated 10/31/04