UMBC CMSC 313, Computer Organization & Assembly Language, Fall 2003, Section 0101

Cache Memory & Interrupts

Tuesday 10/14, 2001

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Assigned Reading in Murdocca & Heuring:  7.6

Assigned Reading in Neveln:  9.1-9.8

Assigned:   

Due:  (Project 4 due date extended to Thu 10/16)

Topics Covered:

• Slides are available in PDF: Slides14.pdf
• Memory cache: bridges fast CPU and slow system bus, cache read/write policy.
• Different cache mapping schemes: associative, direct, set associative.
• Quick look at interrupts: interrupts versus polling, the role of the interrupt controller, different events that cause an interrupt.