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This lecture uses Intel documentation on the IA-32 Architecture.
In principal this covers all Intel 80x86 machines up to and including
the Pentium 4. Stored locally in order to minimize network traffic.
First look over Appendix B. (This is a .pdf file that your
browser should activate acroread to display. Look on the left
for a table of contents and ultimately click on Appendix B.
Intel IA-32 Instructions(pdf)
Note the "One Byte" opcodes. There are two tables with up to 128
instruction operation codes in each table.
Then move on to the "Two Byte" opcodes. The first opcode byte would
tell the CPU to look at the next byte to determine the operation code
for this instruction.
Now, move back to Appendix A and see the various formats that
an instruction may have. Consider the choices that would have to be
made by a programmer writing a disassembler for this architecture.
Intel IA-32 Instructions(pdf)
The IA-32 is a CISC, Complex Instruction Set Computer.
This is in contrast to computer architectures such as the
Alpha, MIPS, PowerPC = Power4 = MAC G5, etc. that are
RISC, Reduced Instruction Set Computer. "Reduced" does not
mean, necessarily, fewer instructions. "Reduced" means
lower complexity and more regularity. Typically all instructions
are the same number of bytes. Four bytes equals 32 bits is the most
popular. Regular in the sense that all registers are general
purpose. Not like the IA-32 using EAX and EDX for multiply
and divide.
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