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There are many simulation and design tools available for digital logic.
Some sections of CMSC 313 use B2Logic.
This is a graphical interface program for use on Microsoft Windows.
This program has many building blocks from the digital logic of
the 1970 era. In this era dual in line packages had many 4-bit
circuits. B2Logic allows a maximum of a 16 bit bus as a primitive.
This is a practical learning tool for simple logic circuits, yet it
can not handle todays designs, 32-bit and 64-bit computer architectures.
Some sections of CMSC 313 use DigSim a Java applet that can be run
from any WEB browser. DigSim is interactive and dynamic yet seems
limited in circuit complexity and timing accuracy. Learn more at
Richard Chang's WEB page
There are major commercial Electronic Design Automation, EDA, systems
for todays digital logic. Cadence is one of todays major suppliers and
UMBC has Cadence software available on GL computers.
Mentor Graphics, Synopsis and others provide large tool sets.
Altera and Xilinx are major providers of software for making custom
integrated circuits using Field Programmable Gate Arrays, FPGA.
www.altera.com
Altera has a downloadable student version.
www.xilinx.com
The student version of Xilinx came with your textbook. Be sure
to install CD-Rom 2 of 2 first, if you wish to try this software.
The best WEB site to find free EDA tools is www.geda.seul.org
For projects for this section of CMSC 313 we will use Cadence VHDL
that is available on linux.gl.umbc.edu.
Using Cadence VHDL on Linux.GL machines
First: You must have an account on a GL machine. Every student
and faculty should have this.
Either log in directly to linux.gl.umbc.edu or
Use ssh linux.gl.umbc.edu
You can copy many sample files to your working directory using:
cp /afs/umbc.edu/users/s/q/squire/pub/../download/cs411.tar .
Do not forget the final space dot. There are many files available.
Next: Follow instructions exactly or you figure out a variation.
1) Get this tar file into your home directory (on /afs i.e.
available on all GL machines.)
cs411.tar and then type commands:
cp /afs/umbc.edu/users/s/q/squire/pub/../download/cs411.tar .
tar -xvf cs411.tar
cd vhdl
mv Makefile.cadence Makefile
source vhdl_cshrc
make
more add32_test.out
make clean # saves a lot of disk quota
Then do your own thing with Makefile for other VHDL files
2) The manual, step by step method (same results as above)
Be in your home directory.
mkdir vhdl # for your source code .vhdl files
cd vhdl
mkdir vhdl_lib # your WORK library, keep hands off
You now need to get the following 6 files into you vhdl directory:
vhdl_cshrc
cds.lib change $HOME to your path if needed
hdl.var
Makefile.cadence for first test
add32_test.vhdl for first test
add32_test.run for first test
mv Makefile.cadence Makefile
# Run the test run:
source vhdl_cshrc
make # should be no error messages
more add32_test.out # it should have VHDL simulation output
make clean # saves on your quota
You are on your own to write VHDL and modify the Makefile.
Remember each time you log on:
cd vhdl
source vhdl_cshrc
make # or do your own thing.
The above is the latest generation Cadence "ldv" "ncvhdl, nceval, ncsim"
FPGA and other CAD information
You can get working chips from VHDL using synthesis tools.
One of the quickest ways to get chips is to use FPGA's,
Field Programmable Gate Arrays.
The two companies listed below provide the software and the
foundry for you to design your own integrated circuit chips:
www.altera.com
www.xilinx.com
Complete Computer Aided Design, CAD, packages are available from
companies such as Cadence, Mentor Graphics and Synopsis.
Other Digital Logic Tool Links
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