[CMSC 411 Home] | [Syllabus] | [Project] | [VHDL resource] | [Homework 1-6] | [Homework 7-12] [files] |
Lec Date Subject Reading Homework assigned due 1. 8/29 Introduction, terminology 1.1-1.6 HW1 8/30 9/4 Optional, VHDL language and constructs 2. 9/5 Performance, 2.1-2.5 9/6 3. 9/10 Benchmarks, 2.6-2.8 HW2 9/11 4. 9/12 CPU operation skim 3.1-3.7 HW1 read p117-121 9/13 5. 9/17 VHDL introduction Ashen 1.1-1.5 HW3 HW2 VHDL web pages 9/18 6. 9/19 Instructions and registers skim 3.8-3.11 read p145-150 9/20 Homework 4 Cancelled 7. 9/24 Arithmetic 4.1-4.4 HW4 HW3 Ashen 8.5 9/25 8. 9/26 ALU 4.5 9/27 9. 10/1 Multiply 4.6 HW5 Ashen 6.1-6.3 10/2 10. 10/3 Divide 4.7 HW4 10/4 11. 10/8 Floating Point 4.8 10/9 12. 10/10 VHDL - circuits and debugging VHDL web pages HW6 HW5 Ashen 18.1-18.2 10/11 13. 10/15 Control Unit 5.1-5.3 10/16 14. 10/17 Microprogramming - review 5.4-5.5 10/18 15. 10/22 mid-term exam 10/23 16. 10/24 Pipelining 1 6.1 HW7 10/25 17. 10/29 Pipelining 2 6.2-6.3 10/30 18. 10/31 Project outline and VHDL VHDL web pages HW8 HW6 * Ashen 5.1-5.5 11/1 19. 11/5 Pipelining hazards 1 6.4-6.6 PROJ HW7 11/6 20. 11/7 Pipelining hazards 2 " HW9 HW8 11/8 21. 11/12 Cache 7.1-7.2 PROJ 1/3 * 11/13 22. 11/14 Cache performance 7.3 HW10 HW9 11/15 23. 11/19 Virtual memory 7.4-7.5 HW11 11/20 PROJ 2/3 * 11/21 Optional, VHDL language and constructs 24. 11/28 I/O types and performance 8.1-8.3 HW12 HW10 11/29 25. 12/3 Busses, I/O-processor connection 8.4-8.6 HW11 12/4 26. 12/5 Multiprocessors skim 9.1-9.4 HW12 12/6 27. 12/10 Review study PROJ 3/3 * 12/11 28. 12/17 Final Exam 0102, 6:00pm-8:00pm (no other) 12/13 Final Exam 0101, 3:30pm-5:30pm (no other) No late homework or project accepted after final exam. * submitted, not graded until next weekend (not late)
Last updated 10/30/01