This year, ``solutions'' won't be provided for each checkpoint. Instead, the project team must get their design to work. Of course, both the instructor and the TA are available to help, both before and after the checkpoint due date. Since solutions won't be forthcoming, it's to your advantage to get as much working as possible before the checkpoint, since you'll get a better grade that way. If you fall behind, you'll have to do more work in less time to catch up.
There are two pieces of advice that'll be crucial to doing well on this project: start early, and get help if you need it. The checkpoints will take some time both to design and to implement. If you start and finish early, you can always take a break right before the assignment is due. If you start late, you may not finish in time. In either case, please get help from the professor or the TA if you're stuck - don't wait until a few days before the checkpoint due date.
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NOTE: assignments on this page are subject to change until they are assigned in class. Assignment dates will be noted under each checkpoint. |
The goal of this checkpoint is to build a 32 bit ALU. This ALU must perform all of the functions needed by the DLX CPU. The ALU has two inputs and a single output, and uses control signals to determine which function it will perform. The coding of the control signals (what to call the signals, and how to set them to generate a specific ALU function) is up to each project group.
The ALU must perform several kinds of functions: arithmetic functions (add, subtract), logical functions (OR, AND, XOR, NOT), comparisons (see the DLX page for a list), and shifts (again, see the DLX page for descriptions). The design may use any simple components (such as AND, NAND, OR, NOR, XOR, inverter, multiplexer, etc.) provided by the logic design program. However, there are a few design restrictions. First, carry lookahead logic must be used at the highest level to connect ALU slices together if there are more than 2 slices (for example, if four 4-bit slices are connected to form a 16-bit slice). In addition, the shifter should be built using a barrel shifter, which will be described in class.
Perhaps the best approach is to build two separate units, one for arithmetic and logic and the other to do shifting. This will be useful later, since your design will require two ALUs - one for the registers and the other for the program counter. Only the ALU used for the registers will need to do shifting.
For this checkpoint, you should have all of the components you'll need to build your CPU. This includes the ALU that you built for checkpoint 1 as well as a 3-ported (two read, one write) register file, single 32-bit register, 32-bit multiplexers, and a simple memory that you can use for testing until you build the cache controller for checkpoint 5. You may use any components you like for this checkpoint. In particular, you'll probably want to create a memory device both for the ``main'' memory and for the register file.
You only have a week for this checkpoint; however, it's also the simplest checkpoint. The only difficulty will be figuring out a way to build a three-port register file from generic memory components (RAM) and making sure that it works as an edge-triggered device. A good way to do this would be to keep two separate copies of the register file. They can both be written on the rising edge, and then each can read the contents of a different register. There are other ways to do this, of course, but this method is likely to be the easiest.
For this checkpoint, you should assemble all of the components into the full datapath. This shouldn't involve a lot of new circuitry - instead, you'll use the ALU and components you've previously designed. The big challenge for this assignment will be putting together a datapath that can execute all of the DLX instructions as well as update the program counter.
Your handin for this checkpoint should include your circuit diagrams (on paper and on disk) and a complete writeup. You need not include detailed diagrams for parts implemented in previous checkpoints such as the ALU and multiplexers. Instead, the circuit diagram should show the high-level connections between those building blocks. The writeup should include a description of how each instruction class will work, detailing the information's path through the datapath. You need not include separate descriptions for instructions that follow the same path (for example, addi and ori use identical paths, differing only in the ALU function selected). This writeup will be crucial for the next step of the project, in which you'll implement the control circuitry.
After completing this checkpoint, your processor should be able to execute programs. The programs may come directly from simple memories (caches are the next project), but they must execute correctly. Thus, the primary goal for this checkpoint is to build the control circuitry for your processor. This probably won't require you to construct any new parts, but will require lots of thinking, writing, and simulating to insure that the existing parts in your datapath work together to execute an instruction.
In addition, to the high-level block diagram of your processor, your handin should include a full description of any state machines and other control logic you used to implement your processor. This might include random logic, PLAs, or ROMs. You should also include some test programs that you ran to test your processor. You need not include detailed descriptions of the parts used to build the processor, such as ALU or register file. Diagrams similar to those shown in Chapter 5 of the text are sufficient.
This is your final checkpoint, and should include your entire design, not just your cache controller.
For the final checkpoint, you'll add a cache controller to your CPU. You may use either a unified cache or a split instruction and data cache. Each cache you implement should hold 64 bytes of data in one word (32 bit) blocks (use 8 16x4 RAM parts for the data) as well as any necessary tags and additional bits. Your cache should use write through. It need not include advanced features such as a write buffer; basic operation is sufficient.
Your cache will interface to the main memory using the bus protocol shown on the main DLX page with two minor changes. First, you need not provide an InstData signal (it will be ignored by the memory). Second, the main memory will have separate lines for data in and out. The main memory circuit will be provided for you (it's now available online), and consists of 4 KB of RAM (valid addresses range from 0x0 - 0xffc, and must be word-aligned). The memory is a circuit in text format; it should be importable into either Mac or PC (please send me e-mail if you have problems). To use the memory, follow this link and save the file you load to ``memory.txt''. Then, load the file into B^2Logic. Of course, you may also use your own memory for testing; however, I'd strongly suggest using the circuit provided.
For this checkpoint, please hand in the high-level circuit diagram for your entire CPU as well as the complete design for your cache (along with a text description of what you did). You should also hand in a listing of any programs you used to test your CPU & cache controller.