University of Maryland Baltimore County

Department of Computer Science and Electrical Engineering

CMPE 411, Fall 2017

Computer Architecture

Tuesday and Thursday 11:30 AM--12:45 PM, ITE 233 

 

Course Information

 Instructor and TA Contact Information  

 Course Syllabus

 Grade structure and policy

 Lecture Schedule

 Assignments

 Projects

 Links

Course Instructor

Dr. Mohamed Younis

Office: ITE 318

E-mail: younis@cs.umbc.edu

URL:    http://www.cs.umbc.edu/~younis

Lab:    Embedded Systems and Networks Lab

Office hours: Tuesday and Thursday (10:30 - 11:30 am)

Research interest:

Wireless Ad-hoc and Sensor Networks, Fault tolerant computing and communication, Real-time systems, Security and Underwater communications, Vehicular networks

Teaching Assistant

Mr. Akram Ahmed

Office: ITE 349B

E-mail: akrama1@umbc.edu

Office hours: Monday and Wednesday (1:00 - 2:00 pm)

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Course Syllabus

Textbook:

Computer Organization and Design, The hardware/software interface, Fifth Edition

David A. Patterson and John L. Hennessy

Morgan Kaufmann Publishers, ISBN 978-0-12-407726-3 978-0-12-374493-7

Course Outline

1. Instruction Set Architecture

•  Instruction formats and semantics

•  Addressing modes

2. Performance Evaluation

•  Measures of performance

•  Benchmarks and metrics

3. Machine Arithmetic

•  ALU design

•  Integer multiplication and division

•  Floating-point arithmetic

4. Processor Design

•  Datapath design

•  Instruction execution and sequencing

•  Hardwired and microcode control

5. Pipelining and Instruction-Level Parallelism

•  Pipelining (Basic Pipeline Operations)

•  Data and Control Pipeline Hazards

• Instruction-Level Parallelism

6. Memory Hierarchy

•  Cache design & evaluation

•  Virtual addressing

•  Performance evaluation

7. Input/Output

•  Types of I/O devices

•  Device access and interface

•  Device control

•  I/O performance

8. Multiprocessing (time permitting)

•  Interconnection networks

•  Programming issues

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Grade Structure and Policy

Course work

Grade distribution

Mid-term Exam

25%

Final Exam

30%

Project

25%

Homework

20%

  •  Five assignments will be given and normalized to %20 of the final grade

  •  Assignments are due in class. Late assignments are not accepted.

  •  Final Exam is comprehensive covering the whole subjects included in the course and discussed in the lectures

  •  The project emphasizes architecture design. It requires writing an architecture simulator using a high level programming language such as C++.

  •  Late projects are not accepted.

  •  Copying/cheating will result in a minimum punishment of a zero grade for the assignment or project.

  •  Academic Integrity Statement:

“By enrolling is this course, each student assumes the responsibilities of an active participant in UMBC’s scholarly community in which everyone’s academic work and behavior and held to the highest standards of honesty.  Cheating, fabrication, plagiarism, and helping others to commit these acts are all forms of academic dishonesty, and they are wrong.  Academic misconduct could result in disciplinary action that may include, but is not limited to, suspension or dismissal.  To find useful information about avoiding plagiarism infractions through appropriate citations, or to read the full policy regarding student academic misconduct for the graduate school, please see http://www.umbc.edu/provost/integrity 

Course grade

Range

A

90% - 100%

B

80% -89.9%

C

70% -79.9%

D

60% - 69.9%

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Lecture notes

Lecture

Date

Subject

1

August 31, 2017

Introduction and overview

2

September 5, 2017

Instruction Semantics and representation

3

September 7, 2017

Addressing Modes & Architectural Design Guidelines

4

September 12, 2017

Performance Evaluation and Metrics

5

September 14, 2017

Performance benchmarks

6

September 19, 2017

Arithmetic Logic Unit

7

September 21, 2017

Multiplier’s Design

8

September 26, 2017

Performing Division

9

September 28, 2017

Floating Point Operations

10

October 3, 2017

Single-Cycle Datapath and Control

11

October 5, 2017

Multi-cycle Processor Design

12

October 10, 2017

Micro-programming and Exceptions

13

October 12, 2017

Introduction to Pipelining

14

October 17, 2017

Pipelined Datapath and Control

15

October 19, 2017

Handling Pipeline Hazards

16

October 24, 2017

Instruction Level Parallelism

17

October 26, 2017

Review

18

October 31, 2017

Midterm Exam

19

November 2, 2017

Dynamic Pipeline Scheduling

20

November 7, 2017

Memory Hierarchy and Cache

21

November 9, 2017

Cache Performance

22

November 14, 2017

Cache Memory (Cont.)

23

November 16, 2017

Virtual Memory

24

November 21, 2017

Virtual Memory (Cont.)

25

November 28, 2017

I/O Systems

26

November 30, 2017

Bus Interconnect

27

December 5, 2017

Interfacing I/O Devices

28

December 7, 2017

Multiprocessor systems

29

December 12, 2017

Review

30

December 14, 2017

Final Exam (10:30AM--12:30PM) 

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Assignments

Assignment

Date Out

Due Date

Assignment #1

September 14, 2017

September 21, 2017

Assignment #2

September 28, 2017

October 5, 2017

Assignment #3

October 10, 2017

October 17, 2017

Assignment #4

October 19, 2017

October 26, 2017

Assignment #5

November 21, 2017

November 28, 2017

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Project

Project

Date Out

Due Date

Term Project

October 26, 2017

December 9, 2017

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Links

·        Cadance VHDL Resources

·         Cadance VHDL Tutorial (Jim Plusquellic)

·        VHDL Tutorial slides (Jim Plusquellic)

·        VHDL Resources in CMPE 315 (Chintan Patel)

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Last Revised: December 12, 2017