`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:42:45 09/10/2010 
// Design Name: 
// Module Name:    nand_latch_tb
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module nand_latch_tb(
    );
//These are the testbench wires and registers that you can manipulate and probe
wire out;
wire out_bar;
reg in; 
reg set;

// Instantiate the latch (named DUT {device under test})
nand_latch DUT(in, set, out, out_bar);

//This initial block will provide values for the inputs
// of the mux so that both inputs/outputs can be displayed
initial 
begin
	in = 0; set = 0;

	#10 set = 1; //set output to 0
	#10 set = 0;

	#10 in = 1;  //output shouldn't change
	#10 in = 0;
	#10 in = 1;
	#10 set = 1; //there we go!

	#10 in = 0;  //since set is 1, we are passing through the input to the output
	#10 in = 1; 
	#10 in = 1;
	#10 in = 0;
	#10			 //wait 10 after in goes to 0
$finish; // to shut down the simulation
end

// this block is sensitive to changes on ANY of the inputs and will
// then display the input, select, and corresponding outputs
always @(in or set)
#1 $display("At in=%b sel=%b out=%h out_bar=%h", in, set, out, out_bar);

endmodule