CMPE 415: Programmable Logic Devices
Spring 2017

Course Information

Course Readings/ Tutorials

Paper/Tutorial Comments
Spartan3e Xilinx board User Guide You need to read this in order to know the FPGA pin locations for LED, switches and clock.
Spartan3e FPGA User Guide You need to read this in order to know about your Spartan3E FPGA features.
The schematic diagrams for the board You need to read this document to know the pin connections in the board.
**New** ISE 14.7 Tutorial You need to read this document to know the pin connections in the board.
A simple tutorial (ISE 13.2)for Verilog module creation and Isim SimulAtor Verilog example files Eight_Bit_Multiplier.v , Eight_Bit_Multiplier_tb.v
Counter example Example of a counter in verilog.
**NEW Full Adder and testbench** Example of a 2-bit fulladder, instantiation in top and testbench in verilog.
Quick reference for verilog Helpful and handy verilog reference.
Verilog according to Tom Helpful intro to verilog. Please also read the accompanying notes.
A simple tutorial for Isim Simulator Steps for running Isim simulator, with Verilog example files nand_latch.v , nand_latch_tb.v
Isim Simulator User Manual Complete Xilinx user manual for Isim simulator.
Xilinx Timing Constraints User Manual Complete manual for adding timing constraints.
Asynchronous FIFO Paper on FIFOs. Concepts, design and Code.

Homework / Projects

All future dates tentative until hwk/project assigned.

Modifications are added

Number Due Date % Hwk/proj grade Material covered and addiotional files
 1  Tue, Feb 14, 1 pm 6.5% learn the fundamental components of the Xilinx FGPA tools required to enter and assemble HDL code using a schematic entry tool and program an FPGA
 2  Saturday, Feb. 25, 11 pm 6.5% Numeric number representation, ADDERS, Verilog, Testbench simulation, testbench template for HW, output file example for Prob.1, Solutions
 3  Sun, March 12 , 11:00 pm 6.5% A game on FPGA, rotator_oneshot.v, pulser.v, random2.v, top.ucf, Highlevel block diagram for HW3, Highlevel solution and block diagram for HW3, some solution design files and testbenches
 4  Thu, March  30th, 1 pm 6.5% Memories, FIFO, Xilinx Core generator.
 5  Thu, April  13th, 11 pm 6.5% Timing, power and FPGA resource analysis
 6  Thu Apr 27, 11:00 pm 6.5% Paddle ball game on FPGA, rotator_oneshot.v, pulser.v, random2.v, top.ucf,
 7   May 11th   1pm % State machine, and image color change and VGA imageRGB2BW.m picture_to_matrix.m parrot128.png smaller sizes of image

Course Topics and Lecture Slides

Future details are tentative.

Date Lecture Topics
Intro: Programmable Logic Devices Course introduction, digital signal processing intro
Verilog 1 Verilog example and sytles, refer to tutorials for more information and sample verilog
Design and Verilog Module Verilog Module
Sign Extension Number representation, sign extension
Blocking nonblocking statement >More Verilog Examples, Blocking nonblocking statement
Fixed-point Number Fixedpoint number reprsentation
Numeric Basics Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
Verilog 2 More Verilog example and sytles, refer to tutorials for more information and sample verilog
Squaring Squaring.
Fixed Input Mults Multipliers.
Verilog Testing Overview of Verilog testing and test benches.
testbench for the sequential multiplier Page1 testbench for the sequential multiplier Page2
*NEW*Sequential Basics & Pipelining Overview of Sequential Logic & Pipelines
Pipelining & Latency Pipelining & Latency
State Machines State Machines and example with verilog
Memories Overview of Memories
Memory and FIFO Examples slides Memory examples
*NEW* Memory and FIFO Examples from book examples from book
look up table ROM verilog look up table or ROM verilog,readmemh
*NEW*FSM and memory examples FSM and memory examples
*NEW* comparator sort comparator, sort example
IP Cores Xilinx Core generator, example
FPGAs 1 FPGAs structures, Spartan3E, FPGA vs ASIC design flow
FPGAs 2 FPGA Design Flow, IO and Timing Constraints, Power Analyser
FPGAs 3 More on Timing Constraints, FFs and latches
Xilinx Xpower Analyzer Overview of Xpower Analyzer, starts from p.15.
Memory Errors & Error Correction Memory errors and correction using Hamming code
fixedpoint conversion in matlab fixedpoint conversion in matlab.
Saturation Overview of Saturation in Verilog.
Rounding Overview of Rounding in Verilog.
FSM and memory examples FSM and memory examples