CMPE 415: Programmable Logic Devices
Spring 2018

Course Information

Course Readings/ Tutorials

Paper/Tutorial Comments
Downloading and Installng ISE 14.7, Licence and Bug Fix Instructions to Install ISE 14.7, Licence and Bug Fix
ISE 14.7 and configuration for Nexys FPGA board Instructions for creating projects in Xilinx ISE 14.7 and Artix-7 board
counter example Download the file and generate the .bit file through xilinx ISE Project Navigator flow to program the Artix-7 FPGA.
A simple tutorial (ISE 13.2 and Spartan board)for Verilog module creation and Isim SimulAtor Verilog example files Eight_Bit_Multiplier.v , Eight_Bit_Multiplier_tb.v
**NEW 2018 ISE14.7 Full Adder and testbench** Example of a 2-bit fulladder, instantiation in top and testbench in verilog. Adder and instantiation tutorial
Quick reference for verilog Helpful and handy verilog reference.
Verilog according to Tom Helpful intro to verilog. Please also read the accompanying notes.
A simple tutorial for Isim Simulator Steps for running Isim simulator, with Verilog example files nand_latch.v , nand_latch_tb.v
Isim Simulator User Manual Complete Xilinx user manual for Isim simulator.
Xilinx Timing Constraints User Manual Complete manual for adding timing constraints.
Asynchronous FIFO Paper on FIFOs. Concepts, design and Code.

Homework / Projects

All future dates tentative until hwk/project assigned.

Modifications are added

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Number Due Date % Hwk/proj grade Material covered and addiotional files
 1  , Feb 12th, 11 pm 6.5% learn the fundamental components of the Xilinx FGPA tools required to enter and assemble submodules to a top module code and demonstrate on FPGAusing VGA Nexys4board manual,VGA: pages14-17 video for demosntration
 2  Sunday, Feb. 25, 11 pm 6.5% Numeric number representation, ADDERS, Verilog, Testbench simulation, Note **: The block diagram needs to show the top system including the connctions and number of CSA blocks and input bits and connection to the CPA. testbench template for HW, output file example for Prob.1, CSA and CPA example and diagram
 3  Mon, March 12 , 11:00 pm 6.5% A game on FPGA, button_debounce.v pulser.v, random2.v, top.ucf, Highlevel block diagram for HW3, Demo
 4  Fri, March  30th, 11 pm 6.5% Memories, FIFO, Xilinx Core generator.
 5  Fri,   , 11 pm 6.5% Timing, power and hardware resource analysis with Xilinx ISE.
 6  Fri, April  27th, 11 pm 6.5% Timing, power and hardware resource analysis with Xilinx Vivado. Vivado install Vivado new file Tutorial Vivado power and timing analysis Vivado IPCore
 7   Phase 1:May 9th   11pm, Phase 2:May 15, 1 pm % State machine, and image color change and VGA imageRGB2BW.m picture_to_matrix.m parrot128.png smaller sizes of image

Course Topics and Lecture Slides

Future details are tentative.

Date Lecture Topics
01/30/2018 Intro: Programmable Logic Devices Course introduction, digital signal processing intro
02/01/2018 Verilog 1 Verilog example and sytles, refer to tutorials for more information and sample verilog
02/06/2018 Design and Verilog Module Verilog Module
02/06/2018 Sign Extension Number representation, sign extension
02/08/2018 Numeric Basics Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
02/15/2018 Blocking nonblocking statement >More Verilog Examples, Blocking nonblocking statement
02/15/2018 Fixed-point Number Fixedpoint number reprsentation
02/08/2018 Numeric Basics Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
02/15/2018 Verilog Testing Overview of Verilog testing and test benches.
02/22/2018 Sequential Basics, Registers and Pipelining Overview of Sequential Logic & Pipelining and example
02/27/2018 Pipelining & Latency Pipelining & Latency
03/01/2018 Registers with Enable and Reset Modeling Registers with additional Reset or Enable signals
03/01/2018 State Machines State Machines and example with verilog
Squaring Squaring.
Fixed Input Mults Multipliers.
Memories Overview of Memories
Memory and FIFO Examples slides Memory examples
*NEW* Memory and FIFO Examples from book examples from book
look up table ROM verilog look up table or ROM verilog,readmemh
*NEW*FSM and memory examples FSM and memory examples
*NEW* comparator sort comparator, sort example
IP Cores Xilinx Core generator, example
FPGAs 1 FPGAs structures, Spartan3E, FPGA vs ASIC design flow
FPGAs 2 FPGA Design Flow, IO and Timing Constraints, Power Analyser
FPGAs 3 More on Timing Constraints, FFs and latches
Xilinx Xpower Analyzer Overview of Xpower Analyzer, starts from p.15.
Memory Errors & Error Correction Memory errors and correction using Hamming code
fixedpoint conversion in matlab fixedpoint conversion in matlab.
Saturation Overview of Saturation in Verilog.
Rounding Overview of Rounding in Verilog.
FSM and memory examples FSM and memory examples