Tinoosh Mohsenin is an Associate Professor in the Department of Computer Science and Electrical Engineering at University of Maryland Baltimore County, where she directs Energy Efficient High Performance Computing (EEHPC) Lab. She received her PhD from University of California, Davis in 2010 and M.S. degree from Rice University in 2004, both in Electrical and Computer Engineering. Prof. Mohsenin`s research focus is on the development of highly accurate high performance processors for signal processing, machine learning, sparse representation and recovery techniques that consume as little energy as possible. Prof. Mohsenin has over 70 peer-reviewed journal and conference publications. She currently leads a number of research projects including the design of next generation wearable biomedical processors, hardware accelerators for deep learning and convolutional neural networks, real time brain signal artifact removal and processing for brain computing interface and assistive devices, which are all funded by National Science Foundation (NSF), Army Research Lab (ARL), Northrop Grumman, Boeing, Nvidia and Xilinx. She has served as associate editor in IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). She was the local arrangement co-chair for the 50th IEEE International Symposium on Circuits and Systems (ISCAS) in Baltimore. She has also served as technical program committee member of the IEEE International Solid-State Circuits Conference Student Research (ISSCC-SRP), IEEE Biomedical Circuits and Systems (BioCAS), IEEE International Symposium on Circuits and Systems (ISCAS) and IEEE International Symposium on Quality Electronic Design (ISQED). She also serves as secretary of IEEE P1890 WG on Error Correction Coding for Non-Volatile Memories.
For current students please refer to EEHPC Team
3. Ali Jafari, PhD, December 2017
Senior Embedded Systems Engineer, Intel Inc.
Thesis title: “An Embedded Multi-Modal Deep Neural Network Processor for Time Series Data Classification”
2. Amey Kulkarni, PhD, February 2017
Senior Embedded Systems Engineer, Velodyne LiDAR Inc.
Thesis title: “Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores”
1. Adam Page, PhD, November 2016
Senior R&D Engineer, Samtec Inc.
Thesis title: “Deploying Deep Neural Networks in Embedded Real-Time Systems”
9. Puranik, Abhilash, “Embedded Low-Power Processor Analysis for Stress Detection,” University of Maryland, Baltimore County, August 2017
8. Kumar Konuru, Sri Harsha, “An EEG Artifact Identification Embedded System using ICA and Multi-Instance Learning,” University of Maryland, Baltimore County, August 2017
7. Abtahi, Tahmid Syed, “Accelerating Convolutional Neural Network with FFT on Embedded Hardware,” University of Maryland, Baltimore County, July 2017
6. Attaran, Nasrin, “Architecture Exploration for Low-Power Wearable Stress Detection Processor,” University of Maryland, Baltimore County, April 2017
5. Sagedy, Christopher, “Development of an Architecture Simulator for the EEHPC Many-Core Processor,” University of Maryland, Baltimore County, December 2015
4. Smith, Emily, “The Design and Implementation of a Scalable Bus-based Cluster with Shared Memory for a Programmable Many-Core Platform,” University of Maryland, Baltimore County, December 2015
3. Viseh, Sina, “A Low Power On-board Processor for a Tongue Assistive Device,” University of Maryland, Baltimore County, August 2014
2. Korde, Asmita, “Detection Performance and Computational Complexity of Radar Compressive Sensing for Noisy Signals,” University of Maryland, Baltimore County, July 2014
1. Chandler, James Darin, “An Efficient Network on Chip Targeted to a Parallel, Low Power, Low-area Homogenous Many-Core DSP Platform,” University of Maryland, Baltimore County, May 2012