opcodes for CS411 project. These are DIFFERENT from MIPS/SGI ISA

                           instruction bits
 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

 0 0 0 0 0 0 -----------------ignored--------------------------- nop

 0 0 0 0 1 0 -----address to bits [27:2] of PC------------------ jump

 1 0 0 0 0 0 x x x x x r r r r r ---2's complement address------ lw r,addr(x)

 1 1 1 0 0 0 x x x x x r r r r r ---2's complement address------ sw r,addr(x)

 0 0 0 0 0 1 a a a a a b b b b b ---2's complement address------ beq a,b,addr+PC

 1 1 0 0 0 0 x x x x x r r r r r ---2's complement address------ ai r,addr(x)

 0 0 0 1 0 0 a a a a a b b b b b r r r r r -ignored- 0 0 0 0 0 1 add r,a,b

 0 0 0 1 0 0 a a a a a b b b b b r r r r r -ignored- 0 0 0 0 1 0 sub r,a,b

 0 0 0 1 0 0 0 0 0 0 0 b b b b b r r r r r -ignored- 0 0 0 1 0 0 cmpl r,b 

 0 0 0 1 0 0 a a a a a 0 0 0 0 0 r r r r r s s s s s 0 0 1 0 0 0 shr r,a by s 

 0 0 0 1 0 0 a a a a a 0 0 0 0 0 r r r r r s s s s s 0 1 0 0 0 0 shl r,a by s

 Definitions:
 nop          no operation, no programmer visible registers or memory
              are changed, except PC <= PC+4

 jump         bits 0 through 25 of the instruction are inserted into PC[27:2]
              probably should zero bits PC[1:0] but should be zero already

 lw r,addr(x) load word into register r from memory location (register x plus
              sign extended addr field)

 sw r,addr(x) store word from register r into memory location (register x plus
              sign extended addr field)

 beq a,b,addr+PC  branch on equal, if the contents of register a are equal
                  to the contents of register b, add the, shifted by two,
                  sign extended addr to the PC (The PC will have 4 added by then)

 ai r,addr(x) add immediate, the contents of register x is added to the
              sign extended address and the result put into register r

 add r,a,b    add register a to register b and put result into register r

 sub r,a,b    subtract register b from register a and put result into register r

 cmpl r,b     one's complement of register b goes into register r

 shl r,a by s shift the contents of register a by s places left and put
              result in register r

 shr r,a by s shift the contents of register a by s places right and put
              result in register r

 Also: no instructions are to have side effects or additional "features"

 Note: assume no other opcodes will be given to your machine, thus take
       advantage of the bits in the opcode (primary and secondary)
       whenever you wish to simplify your circuit

 last updated 8/11/99