Data forwarding example Consider the five stage pipeline architecture: IF instruction fetch, PC is address into memory fetching instruction ID instruction decode and register read out of two values EX execute instruction or compute data memory address M data memory access to store or fetch a data word WB write back value into general register IF ID EX M WB +--+ +--+ +--+ +--+ +--+ | | | | | |-|\ | | | | | | | | /| | \ \_| | | | |PC|-(M)-|IR|-(R) | | / / | |-(M)-| |--+ | | | | ^ \| |-|/ | | | | | +--+ +--+ | +--+ +--+ +--+ | ^ ^ | ^ ALU ^ ^ | | | | | | | | clk-+--------+--------+--------+--------+ | | | +--------------------------+ Now consider the instruction sequence: 400 lw $1,100($0) load general register 1 from memory location 100 404 lw $2,104($0) load general register 2 from memory location 104 408 add $3,$1,$2 add contents of registers 1 and 2, sum into register 3 40C add $4,$3,$1 add contents of registers 3 and 1, sum into register 4 410 beq $3,$4,-100 branch if contents of register 3 and 4 are equal to 314 404 add $3,$3,$3 add ..., this is the "delayed branch slot" always exec. The pipeline stage table with NO data forwarding is: lw IF ID EX M WB lw IF ID EX M WB add IF ID - - EX M WB add IF - - ID - - EX M WB beq IF - - ID - - EX*M WB * becomes nop add IF - - ID EX M WB time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dash represents a stall of the pipeline The pipeline stage table with data forwarding is: lw IF ID EX M WB lw IF ID EX M WB add IF ID - EX M WB add IF ID EX M WB beq IF ID - EX*M WB * becomes nop add IF ID EX M WB time 1 2 3 4 5 6 7 8 9 10 11 a dash represents a stall of the pipeline Note the inherent stall for using data immediately after a load. Note the inherent stall for beq using data from the ALU. The hazard unit must know what the data forwarding unit can do. With data forwarding there is no hazard from the first 'add' to the second 'add' instruction.