// tbmul32c.e  a test circuit for bmul32c
//             uses add32c.e and bmul32c.e files
// changed to test counter = 1 on first stage, b set different

// included is an 8 bit counter to test some 256 cases

// counter8.e a 8 bit counter
// cntr[8] is the 8 bits to be counted
// clk is the system clock      (initialize to 1)
define counter8(cntr[8], clk)
circuits
  cntr[0] <= ~cntr[0] on falling clk;
  cntr[1] <= ~cntr[1] on falling cntr[0];
  cntr[2] <= ~cntr[2] on falling cntr[1];
  cntr[3] <= ~cntr[3] on falling cntr[2];
  cntr[4] <= ~cntr[4] on falling cntr[3];
  cntr[5] <= ~cntr[5] on falling cntr[4];
  cntr[6] <= ~cntr[6] on falling cntr[5];
  cntr[7] <= ~cntr[7] on falling cntr[6];
end circuits;
end counter8;


// main circuit to test the multiplier 
// checking is manual via  tbmul32.run

signal a[32]; // multiplier
signal b[32]; // multiplicand
signal c[64]; // product
signal clk <= #b1; // clock
signal cntr[8] <= #h01; // 8 bit counter to generate test cases
circuits
  clk <= ~clk after 100ns;  // the clock generator, period is 200ns
  cnt use counter8(cntr, clk);
  a[3:0]   <= cntr[3:0];  // some values for a
  a[7:4]   <= cntr[3:0];  // some values for a
  a[11:8]  <= cntr[3:0];  // some values for a
  a[15:12] <= cntr[3:0];  // some values for a
  a[19:16] <= cntr[3:0];  // some values for a
  a[23:20] <= cntr[3:0];  // some values for a
  a[27:24] <= cntr[3:0];  // some values for a
  a[31:28] <= cntr[3:0];  // some values for a
  b[3:0]   <= cntr[3:0];  // some values for b
  b[7:4]   <= cntr[3:0];  // some values for b
  b[11:8]  <= cntr[3:0];  // some values for b
  b[15:12] <= cntr[3:0];  // some values for b
  b[19:16] <= cntr[3:0];  // some values for b
  b[23:20] <= cntr[3:0];  // some values for b
  b[27:24] <= cntr[3:0];  // some values for b
  b[31:28] <= #b0001;     // some values for b

  mul use bmul32c(a, b, c);

end circuits;