Example method for HW12 (different numbers!) 64 bit wide bus, clocked ============================================================== | | address and | two 32-bit data address and | two 32-bit data word count | words sent word count | words received received in | in one clock sent in one | in one clock one clock | clock | | | +-----+-----+-----+-----+ +-----+-----+ +->| | | | |Registers | I/O device| | +-----+-----+-----+-----+ | receiving | | | RAM memory that is | | word-count| 30clk| four 32-bit words wide| | words of | | | and has output | | data | +-<| registers for four | +-----------+ | words | +-----------------------+ A memory on a bus has the following specification: 30 cycle memory access for first access for a new address, new transaction. 20 cycle memory access for each additional sequential access. Memory access starts immediately after the previous memory access completes. The bus is 64-bits wide, synchronous, and has a clock of 100 MHz. Words are 32-bits, thus two words go on the bus at the same time. Every transaction must end by putting two idle signals on the bus. Words and idles going on the bus overlap memory access. Bus speed does not count the clock time to read the address. Three cases are presented. A bus is to send 256 words in 4 word blocks, thus 64 transactions. #################################### Bus timing: clock cycle action 1 address (don't count) 2- 31 memory access 1 30 cycle memory access 32 w1,w2 on bus non-overlapping bus transfers 33 w3,w4 on bus 34 required bus idle 35 required bus idle (but, subtract 1 for no address time) (end of transaction.) ... 63 more transactions, same as above + 4 is two w12 on bus and w34 on bus plus 2 more for idle, idle 1*30 + 4 = 34 clock cycles 64 transactions * 34 = 2176 clocks assuming a 100 MHz clock, time = 1/F = 10 ns total time = 2176 clocks * 10 ns = 21,760 ns = 21.76 microseconds 64/21.76 = 2.95 M transactions per second Total bytes = 256 words * 4 bytes per word = 1024 bytes 1024/21.76 = 47 MB per second bandwidth ----------------------------------------------------------------------------- A bus is to send 256 words in 16 word blocks, thus 16 transactions. ##################################### clock cycle action 1 address (don't count) 2- 31 memory access 1 30 cycle memory access 32- 51 memory access 2 20 cycle memory access starts immediately 32 w1,w2 on bus overlapping bus transfers 33 w3,w4 on bus 34 required bus idle 35 required bus idle 52- 71 memory access 3 20 cycle memory access 52 w5,w6 on bus overlapping bus transfers 53 w7,w8 on bus 54 required bus idle 55 required bus idle 72- 91 memory access 4 20 cycle memory access 72 w9,w10 on bus overlapping bus transfers 73 w11,w12 on bus 74 required bus idle 75 required bus idle 92 w13,w14 on bus non-overlapping bus transfers 93 w15,w16 on bus 94 required bus idle 95 required bus idle (but, subtract 1 for no address time) (end of transaction.) ... 15 more transactions, same as above 1*30 + 3*20 + 4 = 94 cycles (for 1 transaction) 16 transactions * 94 = 1504 clocks assuming a 100 MHz clock, time = 1/F = 10 ns total time = 1504 clocks * 10 ns = 15,040 ns = 15.04 microseconds 16/15.04 = 1.06 M transactions per second Total bytes = 256 words * 4 bytes per word = 1024 bytes 1024/15.04 = 68 MB per second bandwidth ____________________________________________________________________________ A bus is to send 256 words in one 256 word block, thus 1 transaction. ####################################### clock cycle action 1 address (don't count) 2- 31 memory access 1 30 cycle memory access 32- 51 memory access 2 next access starts immediately 32 w1,w2 on bus overlapping bus transfers 33 w3,w4 on bus 34 required bus idle 35 required bus idle 52- 71 memory access 3 20 cycle memory access 52 w5,w6 on bus overlapping bus transfers 53 w7,w8 on bus 54 required bus idle 55 required bus idle ... 1272- 1291 memory access 64 (last) 20 cycle memory access 1272 w249,w250 on bus bus transfers from previous access overlap 1273 w251,w252 on bus 1274 required bus idle 1275 required bus idle 1292 w253,w254 on bus last four, no more overlap with memory access 1293 w255,w256 on bus 1294 required bus idle 1295 required bus idle (but, subtract 1 for no address time) (end of transaction.) 1*30 + 63*20 + 4 = 1294 cycles assuming a 100 MHz clock, time = 1/F = 10 ns total time = 1294 clocks * 10 ns = 12,940 ns = 12.9 microseconds 1/12.9 = 0.08 M transactions per second Total bytes = 256 words * 4 bytes per word = 1024 bytes 1024/12.9 = 79 MB per second bandwidth