From my duplicate bridge days: "Many beggars are walking the
  streets of London, who neglected to clear trump".

  From design days: "Many digital logic designers are unemployed,
  who neglected using the clear signal".
  (This should be the only place to use    miss <= '0';)

  later
   miss <= '1', '0' after 30 ns; -- sets miss to 1 for 30 ns

  Beware VHDL  hwrite, it prints zeros for "U" undefined, and
  "X" unknown or conflict.

  Out parameters can not be tested.

  Signals in a process, are set upon exiting the process.
  (You can not set a signal then test it, only works with variables.)


  Signals remain, unless changed, from one process execution
  to the next. (Your local copy of miss must have a different
  name and must be a signal, not a variable.)

  Variables are temporary, just usable within one process
  execution. Declare variables inside the process, set them,
  test them, normal programming. But! if the same values
  are needed outside the process, make a slightly different
  name for a signal, and set both the variable and the signal.

  If you execute  miss <= '1', '0' after 30 ns; again before
  30 ns you will get a don't know, 'X' on miss.
  sclk <= something with miss or clk;  becomes 'X'.
  Registers will output x"XXXXXXXX" as  x"00000000" yet
  the output is garbage. Thus, guard your "miss" code and
  do not execute that code while in a "my_miss" state.
  Thus:
  signal my_miss : std_logic := '0';
  When you set miss, also set my_miss.
  my_miss := '1', '0' after 30 ns;  -- you can test this

  Ugh! You may have to adjust timing, 30 to 28, or 24,
  it depends on your logic and if you are using my
  cache_memory entity.