CMPE 212 Fall 2023
  • CMPE 212 - Digital Analysis and Design
  • UMBC, Spring 2023


*** FINAL EXAM on WED 24-th May 2023 from 1 to 3 PM in *** SOND 112 ***
Please note the class room change for the final exam: It will be in SOND 112 instead of the regular class room.


*** It turns out that the lab 12 description that was posted is WRONG ***
This was explained and discussed at length in class on Monday 8th May 2023
It was pointed out that VLSI level CAD tools or even architecture level CAD tools will not catch this type of
glaring mistake in the design of a sequential machine.
For (a small amount of) extra credit: try to find out if there is a simulator/emulator that will catch this type of design flaw.

Obviously lab 12 is now canceled, you need not write reports for that lab.
Those who already submitted reports will get (a small amount of) extra credit.

The last lab session time-slot on Friday 12th May 2023,   can be used to complete any prior labs
(from lab 1 to lab 11, in case anyone has not yet completed any of those previous experiments.)


Lab 11 description is posted at the link below:
Lab 11: State Machine Design and Implementation

Lab 10 description is posted at the link below:
Lab 10: Bidirectional Shift Register



** EXAM on Monday 10th April 2023 in class, during the class time-slot **
It is an open book, open notes, open laptops, ... open everything exam.
However, it is an individual exam;
so do not discuss with or copy anything from other students in the class.



Lab 1 is scheduled on Friday 3 rd Feb. 2023. The description is posted at the link below:
Lab 1: Introduction to the lab equipment: Multimeter, Power Supply, Resistors, and Breadboards

Lab 2 description is posted at the link below:
Lab 2: Integrated Circuits and Binary Code Conversion

Lab 3 description is posted at the link below:
Lab 3: Switching Expressions

Lab 4 description is posted at the link below:
Lab 4: DeMorgans Laws

Lab 5 description is posted at the link below:
Lab 5: Adders

Lab 6 description is posted at the link below:
Lab 6: The 7-Segment Display; Simultaneous Minimization of multiple switching functions using the QM Method.
The part of Lab 6 to be completed at home (Due on Friday 17 th March)

As decided at the end of the last class this week (which was yesterday = wed 15th march 2023)
There will be no new lab experiment to be done (or new material to be covered) tomorrow = Fri 17th March 2023

However, the Lab will be open at the regular weekly time and the TA will be available for help; in case you (= the students)
want to complete experiments of parts thereof; IF ANY; that are still incomplete.

Lab 7 Addendum is posted at the link below:
Lab 7 Addendum

Lab 8 description is posted at the link below:
Lab 8: SR Latch

Lab 9 description is posted at the link below:
Lab 9: Logic Hazards




  • Dhananjay S. Phatak
  • Office:
    ITE 327
  • Phone:
    410-455-3624
  • Email:
    phatak@umbc.edu

Lectures Time and place

Monday and Wednesday 1 pm --- 2:15 pm     in room 104 in the Math & Psychology Building.

Lab session(s)

Session 1: Friday 9 am to 10:50 am.     
Session 2: Friday 11 am to 12:50 am.     

Instructor Office Hours

Tue and Wed 2:30 -- 3:30 pm, or by appt.

TAs



Textbook

  • Digital Logic Circuit Analysis and Design
    by Victor P. Nelson, H. Troy Nagle, Bill D. Carroll,
    and J. David Irwin, Prentice Hall, 1995.

Other Reference Material

  • Switching and Finite Automata Theory
    by Zvi Kohavi, McGraw Hill, 1978
    This is a classic book on switching theory.
  • Verilog
    There are a Large Number of Tutorials and Guides Available Online.

Topics to be Covered

  • Introduction
  • Number Systems and Codes (Ch.1)
  • Combinational Logic: Switching Algebra, Simplification, Hazards, etc. (Ch.2/3)
  • Combinational Logic: Design Practices and Examples (Ch.4/5)
  • Sequential Logic (Ch.6)
  • Sequential Logic: Design Examples (Ch.7)
  • Analysis, Simplification and Synthesis of Sequential Logic (Ch.8/9)

Evaluation

  • Labs 30% (Open the Labs tab for more info.)
  • Homeworks 10%
  • Midterm Exam : 25%
  • Final (cumulative) 35%

Goals of the Course

To develop an understanding of the fundamentals of digital logic analysis and synthesis.



Introduction
Number Systems and Codes pt.1
Number Systems and Codes pt.2
Number Systems and Codes pt.3
Combinational Logic: Boolean Algebra
Combinational Logic: Switching Algebra and Switching Functions
Switching Circuits
Combinational Logic Minimization: K-maps pt.1
Combinational Logic Minimization: K-maps, QM
Combinational Logic Minimization : Covering, Multiple Outputs, Hazards
Modules : Decoders, Encoders, Muxes, Comparators, Adders
Example of Modular Design: Bit Slicing
Programmable Logic Devices pt.1
Programmable Logic Devices pt.2
Sequential Circuits: Intro, latches and Flip Flops part 1
Sequential Circuits: Flip Flops pt.2
Sequential Circuits: Flip Flops pt.3
Modular Sequential Logic: Shift Registers, etc.
Modular Sequential Logic: Counters part 1
Modular Sequential Logic: Counters part 2
Analysis of Sequential Circuits
Synthesis of Sequential Circuits