Extra Credit 3

CMSC 411 / Olano, Spring 2012

This extra credit deals with the MIPS R4000. It has the eight-stage pipeline shown below.

1. What is the ideal pipeline speedup for this processor?
2. Pipeline startup/drain time and hazards can prevent you from achieving the ideal speedup. Draw the multicycle pipeline diagram for a sequence of one load, eight R-type instructions, and one store. Include required stall cycles that cannot be overcome by forwarding, as well as lines indicating all possible forwarding paths to avoid data hazards. If you don't remember, a multicycle pipeline diagram looks like this:

addui IF IS RF EX DF DS TC WB
addui    IF IS RF EX DF DS TC WB