Naghmeh Karimi

Assistant Professor
Department of Computer Science and Electrical Engineering
University of Maryland, Baltimore County (UMBC)

Book Chapter

1. N. Karimi and Z. Navabi, "VHDL-AMS Hardware Description Language," In The VLSI Handbook, 2nd Edition, Chapter 91, Section XIII, CRC Press, USA, 2006.
2. N. Karimi and Z. Navabi, "ASIC and Custom IC Cell Information Representation," In The VLSI Handbook, 2nd Edition, Chapter 93, Section XIII, CRC Press, USA, 2006.
3. N. Karimi and Z. Navabi, "Timing Description Languages," In The VLSI Handbook, 2nd Edition, Chapter 95, Section XIII, CRC Press, USA.


Journal Articles
1. N. Karimi , A. Kanuparthi, X. Wang, O. Sinanoglu, and R. Karri, "MAGIC: Malicious Aging in Circuits/Cores," ACM Trans. on Architecture and Code Optimization (TACO), vol. 12, no. 1, pp. 5.1-5.25, 2015.
2. S. Kannan, N. Karimi , R. Karri, and O. Sinanoglu, "Modeling, detection, and diagnosis of faults in multi-level memristor memories," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp. 822-834, 2015.
3. S. Kannan, N. Karimi , O. Sinanoglu, and R. Karri, "Security vulnerability of emerging non-volatile main memories and countermeasures," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 1, pp. 2-15, 2015.
4. A. DeTrano, N. Karimi , R. Karri, X. Guo, C. Carlet, and S. Guilley, "Exploiting small leakages in masks to turn a second-order attack into a first-order attack and improved rotating substitution box masking with linear code cosets," The Scientific World Journal, vol. 2015, pp. 1-10, 2015.
5. N. Karimi and K. Chakrabarty, "Detection, diagnosis and recovery from clock-domain crossing failures in multi-clock SoCs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 9, pp. 1395-1408, 2013.
6. N. Karimi , M. Maniatakos, C. Tirumurti, and Y. Makris, "On the impact of performance faults in modern microprocessors," Journal of Electronic Testing : Theory and Applications (JETTA), vol. 29, no. 3, pp. 351-366, 2013.
7. N. Karimi , M. Maniatakos, A. Jas, C. Tirumurti, and Y. Makris, "Workload-cognizant concurrent error detection in the scheduler of a modern microprocessor," IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1274-1287, 2011.
8. M. Maniatakos, N. Karimi , C. Tirumurti, A. Jas, and Y. Makris, "Instruction-level impact analysis of low-level faults in a modern microprocessor controller," IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1260-1273, 2011.
9. N. Karimi , A. Alaghi, M. Sedghi, and Z. Navabi, "Online network-on-chip switch fault detection and diagnosis using functional switch faults," Journal of Universal Computer Science (JUCS), vol. 14, no. 22, pp. 3716-3736, 2008.


Conference Papers
1. N. Karimi , J. Danger, F. Lozac'h, and S. Guilley, "Predictive Aging of Reliability of two Delay PUFs," Proc. Int'l Conf. on Security, Privacy and Applied Cryptographic Engineering (SPACE), accepted for publication, 2016.
2. N. Karimi and K. Huang, "Prognosis of NBTI Aging Using a Machine Learning Scheme," Proc. Int'l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2016.
3. X. Guo, N. Karimi , F. Regazzoni, C.Jin, and R. Karri, "Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks," Proc. Hardware-Oriented Security and Trust Symp. (HOST), 2015, pp. 124-129.
4. A. DeTrano, S. Guilley, X. Guo, N. Karimi , R. Karri, "Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack," Proc. Hardware and Architectural Support for Security and Privacy (HASP), 2015, pp. 7:1-7:5.
5. S. Kannan, N. Karimi , and O. Sinanoglu, "Secure memristor-based main memory," Proc. Design Automation Conf. (DAC), 2014, pp. 1-6.
6. S. Kannan, N. Karimi , R. Karri, and O. Sinanoglu, "Detection, diagnosis, and repair of faults in memristor-based memories," Proc. VLSI Test Symp. (VTS), 2014, pp. 1-6.
7. O. Sinanoglu, N. Karimi , J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, "Reconciling the IC test and security dichotomy," Proc. European Test Symp. (ETS), 2013, pp. 1-6.
8. N. Karimi , K. Chakrabarty, P. Gupta, and S. Patil, "Test generation for clock domain crossing faults in integrated circuits," Proc. Design Automation & Test in Europe Conf. (DATE), 2012, pp. 406-411.
9. N. Karimi , Z. Kong, K. Chakrabarty, P. Gupta, and S. Patil, "Testing of clock-domain crossing faults in multi-core system-on-chip," Proc. Asian Test Symp. (ATS), 2011, pp. 7-14.
10. N. Karimi , S. Sadeghi, and Z. Navabi, "Network-on-chip concurrent error recovery using functional switch faults," Proc. Workshop on RTL and High Level Testing (WRTLT), 2010.
11. N. Karimi , M. Maniatakos, C. Tirumurti, A. Jas, and Y. Makris, "Impact analysis of performance faults in modern microprocessors," Proc. Int'l. Conf. on Computer Design (ICCD), 2009, pp. 91-96.
12. M. Maniatakos, N. Karimi , C. Tirumurti, A. Jas, and Y. Makris, "Instruction-level impact comparison of RT- vs. gate-level faults in a modern microprocessor controller," Proc. VLSI Test Symp. (VTS), 2009, pp. 9-14.
13. N. Karimi , M. Maniatakos, Y. Makris, and A. Jas, "On the correlation between controller faults and instruction-level errors in modern microprocessors," Proc. Int'l. Test Conf. (ITC), 2008, pp. 24.1.1-24.1.10.
14. A. Alaghi, M. Sedghi, N. Karimi , and Z. Navabi, "NoC reconfiguration for utilizing the largest fault-free connected sub-structure," Proc. Int'l. Test Conf. (ITC), 2008, pp.1-1.
15. M. Maniatakos, N. Karimi , Y. Makris, A. Jas, and C. Tirumurti, "Design and evaluation of a timestamp-based concurrent error detection method (CED) in a modern microprocessor controller," Proc. Int'l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2008, pp. 454-462.
16. A. Alaghi, M. Sedghi, N. Karimi , M. Fathy, and Z. Navabi, "Reliable NoC architecture utilizing a robust rerouting algorithm," Proc. Int'l East-West Design and Test Symp. (EWDTS), 2008, pp. 200-203.
17. N. Karimi , S. Aminzadeh, S. Safari, and Z. Navabi, "A Novel GA-based high-level synthesis technique to enhance RT-level concurrent testing," Proc. Int'l. Online Test Symp. (IOLTS), 2008, pp. 173-174.
18. A. Alaghi, N. Karimi , M. Sedghi, and Z. Navabi, "Online NoC switch fault detection and diagnosis using a high level fault model," Proc. Int'l. Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2007, pp. 21-30.
19. N. Karimi , S. Mirkhani, Z. Navabi, and F. Lombardi, "RT level reliability enhancement by constructing dynamic TMRs," Proc. ACM Great Lakes Symp. on VLSI (GlSVLSI), 2007, pp. 172-175.
20. N. Karimi , and Z. Navabi, "A dynamic reconfiguration method for error recovery of RT level designs," Proc. Int'l. East-West Design and Test Symp. (EWDTS), 2007, pp. 249-254.
21. N. Karimi , S. Mirkhani, and Z. Navabi, "ESTA: An efficient method for reliability enhancement of RT-Level designs," Proc. Asian Test Symp. (ATS), 2006, pp. 195-202.
22. N. Karimi , P. Riahi, and Z. Navabi, "A survey of testability measurements at various abstraction levels," Proc. North Atlantic Test Workshop (NATW), 2003, pp. 26- 33.
23. P. Riahi, Z. Navabi, N. Karimi , and F. Lombardi, "A VPI-based IP core serial fault simulation and test generation methodology," Proc. North Atlantic Test Workshop (NATW), 2003, pp. 96-103.


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