UMBC CMSC 313, Computer Organization & Assembly Language, Spring 2002, Section 0101
More Finite State Machine Design
Tuesday 05/07, 2001
Assigned Reading in Murdocca & Heuring:
Assigned Reading in Neveln:
Assigned: DigSim 3
- The state reduction algorithm given in the last lecture takes
O(n4) time for a finite state machine with n states because
there are O(n2) pairs of states and we make at most
O(n2) passes. (During each pass other than the final pass,
at least one pair of states is found to be distinguished. So, there
cannot be more than n2 passes.) A more clever implementation
of the algorithm will result in an O(n2) running time.
- After reducing the number of states in a finite state machine,
we must still assign a unique bit pattern to each state. This is the
state assignment problem. We went over an example where using a
different state assignment leads to a much simpler combinational
circuit for a finite state machine. Unfortunately, there's no way to
find the "best" state assignment other than trying all n!
possibilities. Instead, people follow heuristics ("rules of thumb")
to solve the state assignment problem.
Some heuristics for the state assignment problem
(from Digital Design: Principles and Practices 2/e,
John F. Wakerly, Prentice-Hall, 1994).
- The initial state should be simple for the reset
operation --- i.e., all zeroes or all ones.
- Minimize the number of state variables that change
on each transition.
- Maximize the number of state variables that don't
change on each transition.
- Exploit symmetries in the state diagram.
- If there are unused states (when the number of states s
is not a power of 2), choose the unused state variable
combinations carefully. (Don't just use the first s
combination of state variables.)
- Decompose the set of state variables into bits or fields
that have well-defined meaning with respect to the input
or output behavior.
- Consider using more than the minimum number of
states to achieve the objectives above.
- We took our good friend the sequence detector through the two
steps of state reduction and state assignment. Our textbook gives
the circuitry for the sequence detector after reducing the 7-state
machine to a 6-state machine. However, the simplified SOP formulas
obtained from the 6-state machine is actually worse than those
we obtained from the 7-state machine
last time. We changed the state assignment for the 6-state
machine and obtained SOP/POS formulas that were better than
the ones from the 7-state machine.
- We discussed excitation tables and how to implement a finite
state machine using J-K flip-flops. Sometimes using a J-K flip-flop
instead of a D flip-flop results in a smaller circuit. This is
because the excitation table for J-K flip-flops has many "don't
cares". However, the additional cost for wiring the 2 inputs for
each J-K flip-flop (instead of 1 input for a D flip-flop) has made D
flip-flops more popular, because the cost of wiring is a significant
consideration in many applications.
- Handed out and discussed DigSim Exercise
14 Nov 2003 10:17:29 EST
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