UMBC CMSC 313, Computer Organization & Assembly Language, Spring 2002, Section 0101

More on Interrupts

Thursday 03/14, 2001

Up]

Assigned Reading in Murdocca & Heuring:  5.1-5.3

Assigned Reading in Neveln:   

Assigned:   

Due:   

Topics Covered:

• Recap interrupts.
• Hardware vs Software interrupts.
  • Hardware: I/O, clock tick, power failure, exceptions
  • Software: INT instruction.
• Types of Hardware Interrupts.
  • External vs Internal
    External: generated by CPU's interrupt pin
    Internal (exceptions): div by zero, single step, page fault, bad opcode, stack overflow, protection, ...
  • Synchronous vs Asynchronous
    Synchronous: occurs at exactly the same place every time the program is executed. E.g., bad opcode, div by zero, illegal memory address.
    Asynchronous: occurs at unpredictable times relative to the program. E.g., I/O, clock ticks.
• A typical sequence of events during an interrupt.
  • Device sends signal to interrupt controller.
  • Controller uses IRQ# for interrupt # and priority.
  • Controller sends signal to CPU if the CPU is not already processing an interrupt with higher priority.
  • CPU finishes executing the current instruction
  • CPU saves EFLAGS and return address on the stack.
  • CPU gets interrupt # from controller using I/O ops.
  • CPU finds "gate" in Interrupt Description Table.
  • CPU switches to Interrupt Service Routine (ISR). This may include a change in privilege level. IF cleared.
  • ISR saves registers if necessary.
  • ISR, after initial processing, sets IF to allow interrupts.
  • ISR processes the interrupt.
  • ISR restores registers if necessary.
  • ISR sends End of Interrupt (EOI) to controller.
  • ISR returns from interrupt using IRET. EFLAGS (inlcuding IF) and return address restored.
  • CPU executes the next instruction.
  • Interrupt controller waits for next interrupt and manages pending interrupts.
• Stacks and interrupts.