## Homework

#### Homework 1 (due Thu 09/06)

Available in PDF: hw1.pdf.

#### Homework 2 (due Thu 09/13)

Available in PDF: hw2.pdf.

#### Homework 3 (due Tues 11/27)

Available in PDF: hw3.pdf.

#### Homework 4 (due Tues 12/04)

1. Consider the finite state machine below:

1. Complete the state transition table for this finite state machine, using the state assignment: A = 000, B = 010, C = 001, D = 110, E = 011 and F = 111. (Note that two bit patterns are not used.)

Use this table: hw4-1.pdf.

2. Write out a Boolean expression for s2', s1', s0' and z. Start with either the disjunctive normal form (a.k.a. sum of products) or the conjunctive normal form (a.k.a. product sums). Simplify the formula as much as you can and write down your final answer below the table in hw4-1.pdf. Show all your work in separate sheets of paper.

3. Construct the finite state machine in Logisim using three D flip flops to store the state. Save your circuit, transfer the file to GL and submit using: submit cs313 hw4 hw4-1.circ

4. Turn in your paper-based work (parts a & b, including work for part b) in class.

2. For this question, you will construct a modulo 10 counter. That is your finite state machine will "count" from 0 to 9 with each clock tick. After it has counted 9, the machine should cycle back to 0.

1. Complete the state transition table for your modulo 10 counter. Since 10 is between 8 and 16, you will need 4 bits to count from 0 to 9. Use the natural state assignment, that is 0 should be 0000, 1 should be 0001, ... 5 should be 0101 ... and 9 should be 1001.

Use this table: hw4-2.pdf.

2. Write out a Boolean expression for s3', s2', s1' and s0'. As in Question 1, show all your work and write down your answer below the table in hw4-2.pdf.

3. As in Question 1, implement your finite state machine in Logisim. Use D flip flops, you should have 4 flip flops. Then, save and submit the circuit file on GL: submit cs313 hw4 hw4-2.circ

4. Turn in your paper-based work (parts a & b, including work for part b) in class.

#### Homework 5 (due Tues 12/11)

You must submit your paper-based work in class and your Logisim implementations on-line.

1. Extend the modulo 10 counter you constructed in Homework 4 with two 7-segment displays:

This display should display the numbers from 1 to 10 and then cycle back to 1. (Note: this is off-by-one from the 0 through 9 stored in the flip flops.)

Use the following table to determine the formulas you should use for each segment of the display: hw5-1.pdf.

Note that you only need 8 output variables, since the 7-segment display for the ten's place either shows 1 or nothing. Use the output variables o1 through o8 as indicated below the truth table. Show how you derived and simplified the Boolean formulas for each output variable. Turn in your table and your work on paper in class.

Implement your counter with 7-segment displays in Logisim. Then, save and submit the circuit file on GL:

submit cs313 hw5 hw5-1.circ

2. For this problem, you will add two instructions to a version of the 2-bit CPU shown in class:

In this version of the 2-bit CPU, each register has its own MUX for its input. These are labeled R0MUX and R1MUX. As before, these MUXes will select input from either Reg0 (00), Reg1 (01), Immediate Operand (10) or ALU Output (11). To store the result in one register, its MUX must be enabled. To make sure that the other register holds its current values, the other register's MUX must be disabled.

For example, to direct the ALU output to Register 1, R1MUX must be enabled and its select bits set to 11. Also, R0MUX must be disabled (its select bits can be set to anything.) In the circuit above, the control wires for R0MUX and R1MUX are bundled into 3-bit wide wire bundles. The enable bit is bit 0. Thus, we can set the R0MUX lines to 110 and the R1MUX lines to 111. (Actually, R0MUX can be xx0.) You can test this out in the existing circuit by disconnecting the R0MUX and R1MUX lines from the Instruction Decoder and connect them to the R0MUX Test and R1MUX Test input pins. Then you can manually enter the settings and check the correctness.

With 2 MUXes instead of just one, this version of the 2-bit CPU can implement two instructions that were not possible before:

• EXCHG (exchange): swap the values of Register 0 and Register 1.
• RESET: store 00 in both Register 0 and Register 1.

Use the instruction code 101x xxxx for the EXCHG instruction and 110x xxxx for the RESET instruction. See lecture slides Slides25.pdf for a description of the instruction code format.

Use this table: hw5-2.pdf. Most of the table has been filled out for you. You just have to fill in the table for the EXCHG and RESET instructions. Then, use the table to derive formulas for the settings for R0MUX and R1MUX. Turn in your table and your work on paper in class.