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|Declarations |Delay, Events |Reserved Words |Operators |System Tasks |Compiler Directives |

Verilog Operators and Special Characters

+    addition
-    subtraction
*    multiplication
/    division
**   exponentiation
%    modulus
>    greater than relation         // relations are 0 if false
<    less than relation            // 1 if true and possibly x
>=   grater than or equal relation
<=   less than or equal relation
==   logical equality relation 
!=   logical inequality relation
===  case equality   // x must match x, z must match z
!==  case not equal  // comparison is made bit-wise
&&   logical and
||   logical or
!    logical negation
&    bit-wise and (also unary reduction and)
~&   unary reduction nand
|    bit-wise or (also unary reduction or, event or)
~|   reduction nor
^    bit-wise exclusive or (unary reduction xor)
~^   bit-wise equivalence (^~) (also unary reduction xnor)
~    bit-wise complement 
>>   bit-wise logical right shift
<<   bit-wise logical left shift
>>>  bit-wise arithmetic right shift
<<<  bit-wise arithmetic left shift
? :  condition ? value-if-true : value-if-false
?    compare equal on this bit
*    compare equal on group of bits
=    substitution
<=   non blocking substitution
:    separator
,    separator
.    selector  .parameter(actual)  module_name.local_name  
;    statement terminator

( )  grouping parenthesis, module instantiation, function and task call
[ ]  subscript, range as in [31:0]
{ }  concatenation
" "  pair of quotes around strings

@    event control
`    compiler directive
$    system task and functions

/*   start comment
*/   end comment
//   start comment to end of line
(*   start non simulation attribute
*)   end non simulation attribute

'    constant  width'radix value  base is b B d D h H o O 
%    format indication b B c C d D e E f F g G h H l L m M o O
                           s S t T u U v V z Z  %10.5E  %0d
\    escape sequences, quoted characters in strings \n \t \\ \" \ddd %%

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