|Option||Description||+accnoerr||Suppresses error message reporting from PLI access routines.||+accu_path_delay||Specifies an alternative path delay algorithm for any module output for which there is a path delay specification.||+alt_path_delays||Calculates the path delay schedule time based on the transistion from the current output value, rather than the transition from the pending scheduled transition value.||+annotate_any_time||Allows SDF backannotation to occur at times other than time 0.||+autonaming||Generates names for any instances of Verilog-XL standard and user-defined primitives that you did not name.||+autoprotect||Protects all modules and UDPs in a source description.||+caxl||Simulates the continuous assignments in your design using the XL algorithm.||+compat_twin_turbo||Ensures the compatibility of the results when using different twin turbo levels. Without this option, for example, results may be different when using the second level Turbo mode (+turbo+2) and the corresponding Twin Turbo level (+turbo+2 with +twin_turbo).||+define<+macro_name>*
Defines text macros, overriding the definitions of duplicate text
macros in the source code. Text macros defined this way are empty
unless immediately followed by their definitions.
If you want to override a text macro with +define+, and give the macro a definition that is quoted, such as "AS" or "file1.shm", you can enclose the definition in single quotes and escape each double quote with a backslash, as follows:
verilog +define+modifier='\"AS\"' +define+file='\"file1.shm\"'
|+delay_mode_distributed||Specifies the distributed delay mode for your simulation.||+delay_mode_path||Specifies the path delay mode for your simulation.||+delay_mode_unit||Specifies the unit delay mode for your simulation.||+delay_mode_zero||Specifies the zero delay mode for your simulation||+err_line_length+<num>||Specifies the maximum number of characters displayed in error messages. You must supply a value with this option. If you specify a value of less than 20 characters, a warning message is issued and the value is set to 80 characters.||+gui||Invokes Verilog-XL in the SimControl window of the SimVision graphical environment.||+incdir+<include_directory>||
Specifies the directories that Verilog-XL searches for the files that
you specify with the `include
Specifies library directory file extensions.
|+libnonamehide||Directs Verilog-XL not to append character strings to any of the definition names in library directory files. Verilog-XL reads only the necessary module and UDP definitions (as it writes them in the file without appending character strings) to resolve instances.||+liborder||Scans libraries and directories as they follow on the command line and then wraps around to the preceding libraries that Verilog-XL has not yet visited. The behavior of this option depends on whether the undefined instance is located in a source file, library file, or a file within a library directory.||+librescan||Scans library files and directories to resolve all undefined module and UDP instances from source files and libraries. The behavior of this option depends on whether the undefined instance is located in a source file, library file, or a file within a library directory.||+libverbose||Displays or prints information about the opening of files and about the resolution of module and UDP definitions during the scanning of libraries.||+licq_all||
Allows simulations to be queued and automatically activated as the
following licenses become available:
||+licq_lmchwif||Allows simulations to be queued and automatically activated as the VXL-LMC-HW-IF license becomes available. The VXL-LMC-HW-IF license is activated during compilation whenever there is a LMSI (LMC hardware interface) system task, $lm_*(), present in the design.||+licq_ncv||Allows simulations to be queued and automatically activated as the NC_VERILOG_SIMULATOR license becomes available.||+licq_turbo||Allows simulations to be queued and automatically activated as the VXL-TURBO license becomes available.||+licq_vxl||Allows simulations to be queued and automatically activated as the VERILOG-XL (Verilog-XL Logic Simulator) license becomes available.||+listcounts||Enables the $listcounts system task, which is disabled by default to accelerate simulation.||+loadpli1||
Dynamically loads a specified PLI 1.0 library from the command line.
Dynamically loads a specified VPI library from the command line.
|+maxdelays||Selects the maximum delays for simulation.||+max_error_count||Specifies the maximum number of error messages displayed or printed during compilation. If the number of errors exceeds the specified number during compilation, an error message is issued and compliation stops. The default number is 200.||+mindelays||Selects the minimum delays for simulation.||+multisource_int_delays||
Provides transport delays with full pulse control and with the ability
to specify unique source/load delays. This option inserts MIPDs on all
single-source nets. This option affects only nets with more than one
Using the +multisource_int_delays option with the +transport_int_delays option provides transport delays with full pulse control for interconnect delays with one or more sources, and provides these delays with the ability to specify unique source/load delays.
|+neg_tchk||Enables negative timing check arguments in the $recovery and $setuphold timing checks. When you do not use the +neg_tchk option, any limits that are negative, either in the description or in backannotation, are set to 0, and a warning is issued.||+no_charge_decay||Ignores all delay specifications for charge decay and all the `default_decay_time compiler directives with a numerical argument in the source description.||+no_cond_event_error||
Causes the following warning message to be issued if you attempt to
condition an event in a timing check with more than one signal;
Warning! Ignoring illegal conditioned event in timing checkIf you attempt to condition an event in a timing check with more than one signal without the +no_cond_event_error option, Verilog-XL issues the following error message and simulation is halted.
Error! Illegal conditioned event in timing check
|+nolibcell||Disables automatic tagging of library modules as cells.||+no_notifier||Prevents notifiers from changing their values to indicate timing check violations. Notifiers are registers passed as arguments to timing checks.||+no_pulse_int_backanno||Prevents PLI backannotation of pulse limits for interconnect delays. Only one warning message is issued on the first attempt at backannotation.||+no_pulse_msg||Disables the display of messages generated by the +pulse_e/n option.||+nosdfwarn||Disables the display of warning messages from the SDF Annotator.||+no_show_cancelled_e||Disables the display of cancelled schedules.||+no_speedup||Disables the default acceleration of behavioral constructs.||+no_tchk_msg||Prevents timing check violation messages from displaying or printing.||+notimingchecks||Disables timing checks.||+no_turbo||Causes the simulation to use a non-Turbo Verilog-XL license.||+nowarn<warn_code>||Disables the display of the type of warning that you specify. You specify the warning type by concatenating its code to the end of the plus option. for example, to disable to the Verilog-TFNPC warning message, issue the +nowarnTFNPC option. You can specify multiple +nowarn options.||+noxl||
Disables the current XL algorithm and applies the XL algorithm that
existed for Verilog-XL Version 1.6c and previous versions.
Note: The -a option invokes the current XL algorithm for the entire design.
|+pathpulse||Enables the PATHPULSE$ specparam which narrows the scope of module path pulse control to a specific module or to a particular set of paths within modules.||+pre_16a_paths||Simulates SDPD conditional paths as if their conditional expressions are always true, which is the behavior of Verilog-XL Version 1.6a and previous versions.||+profile||Enables you to use the behavior profiler in Turbo and Twin Turbo modes, in which the profiler is disabled by default to increase performance.||+protect||Causes Verilog-XL to source protect those regions in a source description that are bounded by the `protect and `endprotect compiler directives. Simulation does not occur.||+pulse_e/n||Sets the value of the module output path to e (error state) and lets the module path output pulse pass through. If you want to specify a separate error state limit for transport interconnect delays, use the +pulse_e/n option for module paths and the +pulse_int_e/n option for interconnect delays.||+pulse_e_style_ondetect||Enables the on-detect style of pulse filtering.||+pulse_e_style_onevent||Enables the on-event style of pulse filtering.||+pulse_int_e/n||Sets the value of the module output path for interconnect delays to e (error state) and lets the module path output pulse pass through.||+pulse_int_r/m||Sets a limit for the rejection of output pulses for interconnect delays.||+pulse_r/m||Sets a limit for the rejection of output pulses. If you want to specify a separate reject limit for transport interconnect delays, use the +pulse_r/m option for module paths and the +pulse_int_r/m option for interconnect delays.||+save_twin_turbo||
Enables the $save system task,
which saves simulation checkpoint files, if you are running in Twin
Turbo mode. Using +save_twin_turbo
increases memory usage by approximately 10%.
Note: You do not need the +save_twin_turbo option to restart the simulation using a previously saved file.
|+sdf_cputime||Logs the number of central processing unit (CPU) seconds that it takes to complete the annotation. The CPU time is written to the log file.||+sdf_error_info||Displays PLI error messages.||+sdf_file
||Specifies the SDF file that the SDF Annotator uses. This plus option overrides the file specified as an argument to the $sdf_annotate system task.||+sdf_nocheck_celltype||Disables celltype validation between the SDF Annotator and the Verilog description. By default, the SDF Annotator validates the type specified in the CELLTYPE construct against the type of the cell instance specified in the INSTANCE keyword construct.||+sdf_noerrors||Disables the display of error messages from the SDF Annotator.||+sdf_nomsrc_int||
If you have no multisource interconnect transport delays (MITDs) in
the design, the +sdf_nomsrc_int
plus option increases performance and reduces memory consumption by
not maintaining information about various interconnects that map to
the same port.
Note: If you have multiple interconnects in the design that map to the same input port, you may not want to use this plus option because the SDF Annotator must resolve these delays using a resolution function prior to annotating the port. The SDF Annotator provides three resolution functions (AVERAGE, MAXIMUM, and MINIMUM). For the SDF Annotator to correctly resolve the delays, it must maintain the interconnect information until the end of annotation.
|+sdf_nowarnings||Disables the display of warning messages from the SDF Annotator.||+sdf_verbose||Writes detailed information about the backannotation process to the annotation log file.||+show_cancelled_e||Displays cancelled schedules.||+splitsuh||Disables the default splitting of $setuphold timing checks into $setup and $hold during compilation. By not splitting the timing checks, you can get a single handle to a $setuphold check and simultaneously change both the $setup and $hold delays using the PLI acc_replace_delays routine.||+switchxl||
Invokes the Switch-XL algorithm to accelerate the simulation of
Note: The Switch-XL algorithm expects all references to the terminals of switches to be expanded. therefore, references to the terminals of switches cannot be references to register bit-selects when the +switchxl option is used.
|+sxl_keep_all||Ensures that the Switch-XL algorithm does not remove any nets from a channel-connected switch network during compilation.||+sxl_keep_declared||Ensures that the Switch-XL algorithm does not remove any explicitly declared nets from a channel-connected switch network during compilation.||+sxl_keep_minimum||Ensures that the Switch-XL algorithm does not remove any net that it does not need for some other purpose from a channel-connected switch network.||+sxl_unidirect||Converts unidirectional switches in a source description to the turn on/turn off delay model. Use this option when you want to invoke Switch-XL and when you do not want unidirectional switches with two kinds of delay timing models.||+trace_twin_turbo||Ensures correct tracing results from Twin Turbo mode, the $settrace system task, the -t option, and the single step (,) command.||+transport_int_delays||Provides transport delays with full pulse control for interconnect delays with one or more sources. Using the +transport_int_delays option with the +multisource_int_delays option provides transport delays with full pulse control for interconnect delays, and it provides those transpoprt delays with the ability to specify unique source/load delays.||+transport_path_delays||Enables full transport delay functionality for module path delays.||+turbo||This option is enabled by default. Improves behavioral simulation performance beyond that of the default Turbo mode by disabling the behavior profiler and the end-of-simulation event count.||+turbo+2||Increases behavioral simulation performance beyond that of the +turbo level by optimizing assignments and by converting scalar nets to compact nets if this conversion accelerates the simulation. This option can also be used with the +twin_turbo option.||+turbo+3||Increases behavioral simulation performance beyond that of the +turbo+2 level by evaluating the right-hand sides of assignments only when the assignments actually occur. This option can also be used with the +twin_turbo option.||+twin_turbo||Generates and uses compiled code for processing the behavioral constructs in the selected Turbo mode (+turbo, +turbo+2, or +turbo+3).||+typdelays||Selects the typical delays for simulation.||+vhdl_arch+<arch_name>||Specifies the name of another VHDL architecture. For example, the option +vhdl_arch+vlib3 specifies the architecture name vlib3.||+vhdl_crshell||Generates a VHDL source file in the current directory consisting of an entity-architecture pair for each of the top-level modules to which the Verilog command line refers. Use this option to generate a shell to import a Verilog HDL design into Leapfrog. No simulation occurs with this option.||+vhdl_verilogic||Sets the port types to the Verilog logic types as defined in the Cadence-supplied VHDL package XL_STD. Without this option, port types are set to the IEEE 1164 types defined in the VHDL package std_logic_1164.||+x_transport_pessimism||Causes an X state for the output in cases in which timing dilemmas are caused by event cancellations that occur when using transport delays or when using the accu_path delay selection algorithm.|
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