Verilog-XL Command-Line Options

Verilog-XL Command-Line Options

You can access information on the following Verilog-XL Version 2.7 features: Back to the Quick Reference main page

Option Description
Overrides the +noxl option and causes the XL algorithm (the default) to accelerate all possible elements of the source description.
(compile only)
Compiles the source text only and then exits. If you use the restart option (-r) with the -c option. Verilog-XL loads the data file but does not perform the simulation.
Prints out a decompilation of the generated data structure after the source text has been compiled and linked, or after a saved data file (see the -r option) has been loaded. This option is mainly for system testing purposes, but you can also use it to decompile a saved data file to find out what it contains, or to recreate a design for which the original source text has been lost.
-f <filename>
(command argument file)
Instructs Verilog-XL to read the text file that you specify following the option. The text file can contain source text filenames and Verilog-XL command options, including other -f options. Nesting is virtually unlimited, but a maximum of 1024 characters has been set to trap recursive -f options.
-i <filename>
(input file)
Allows interactive commands to be read from a file. At the end of this file, interactive commands can be read from the keyboard or other standard input. You must provide the filename following the -i option.
-k <filename>
(key file)
Changes the default key filename (verilog.key) to the name you specify following the -k option. A key file contains standard input.
-l <filename>
(log file)
Changes the default log filename (verilog.log) to the name you specify following the -l option. A log file contains standard output.
Suppresses the display of messages during the major steps in compilation and simulation.
-r <filename>
Restarts the simulator using a data file previously saved with the $save system task. Do not specify source text files on the command line with this option.
Stops the simulator at time 0 after compilation and puts you in interactive mode. You can use the $stop system task in the source description instead of the -s stop option.
Performs a full trace of all simulation events from the start of simulation (same trace as given by the $settrace system task).
Converts all Verilog identifiers to uppercase (in the source code and in interactive mode) to verify that the source description does not rely on case sensitivity.
-v <filename>
(library file)
Tags modules as cells in a library file. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.
(warning suppression)
Suppresses the display of messages that report inconsistencies in module port connections, such as when vector sizes are mismatched or not enough connections have been specified.
(vector net expansion)
Expands all vector nets, except those specified by compiler directives and keywords that control expansion.
-y <directoryname>
(library directory)
Tags modules in a library directory as cells. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.

Copyright 1990-98 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA

Confidentiality Notice No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an information storage/retrieval system) or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc. (Cadence). Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence's customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.