---------------------------------------- -- Basic Computer VHDL Testbench -- Generated by the Basic Computer -- Assembler by Frank Bruno -- Original file: file1 ---------------------------------------- ENTITY test_file1 IS END test_file1; ARCHITECTURE beh_test_file1 OF test_file1 IS COMPONENT basic_comp PORT(clock : IN bit; load : IN bit; start : IN bit; reset : IN bit; address_in : IN integer range 0 to 4095; instr : IN bit_vector(15 DOWNTO 0); inpr : IN bit_vector(7 DOWNTO 0); fgi : IN bit; ar : BUFFER bit_vector(11 DOWNTO 0); ir : BUFFER bit_vector(15 DOWNTO 0); tr : BUFFER bit_vector(11 DOWNTO 0); dr : BUFFER bit_vector(11 DOWNTO 0); i : BUFFER bit; e : BUFFER bit; ac : BUFFER bit_vector(15 DOWNTO 0); ien : BUFFER bit; outr : BUFFER bit_vector(7 DOWNTO 0); fgo : BUFFER bit ); END COMPONENT; SIGNAL clock : bit; SIGNAL load : bit; SIGNAL start : bit; SIGNAL reset : bit; SIGNAL address_in : integer range 0 to 4095; SIGNAL instr : bit_vector(15 DOWNTO 0); SIGNAL inpr : bit_vector(7 DOWNTO 0); SIGNAL fgi : bit; SIGNAL ar : bit_vector(11 DOWNTO 0); SIGNAL ir : bit_vector(15 DOWNTO 0); SIGNAL tr : bit_vector(11 DOWNTO 0); SIGNAL dr : bit_vector(11 DOWNTO 0); SIGNAL i : bit; SIGNAL e : bit; SIGNAL ac : bit_vector(15 DOWNTO 0); SIGNAL ien : bit; SIGNAL outr : bit_vector(7 DOWNTO 0); SIGNAL fgo : bit; BEGIN u1: basic_comp PORT MAP(clock => clock, load => load, start => start, reset => reset, address_in => address_in, instr => instr, inpr => inpr, fgi => fgi, ar => ar, ir => ir, tr => tr, dr => dr, i => i, e => e, ac => ac, ien => ien, outr => outr, fgo => fgo); clock_gen: PROCESS BEGIN clock <= '0' AFTER 40 ns; WAIT FOR 40 ns; clock <= '1' AFTER 40 ns; WAIT FOR 40 ns; END PROCESS; PROCESS VARIABLE state : integer := 0; BEGIN WAIT UNTIL clock'EVENT AND clock = '1'; CASE state IS WHEN 0 => reset <= '1'; start <= '0'; state := 1; WHEN 1 => reset <= '0'; load <= '1'; state := 2; WHEN 2 => address_in <= 0; instr <= "0010000000000100"; state := 3; WHEN 3 => address_in <= 1; instr <= "0001000000000101"; state := 4; WHEN 4 => address_in <= 2; instr <= "0011000000000110"; state := 5; WHEN 5 => address_in <= 3; instr <= "0111000000000001"; state := 6; WHEN 6 => address_in <= 4; instr <= "0000000001010011"; state := 7; WHEN 7 => address_in <= 5; instr <= "1111111111101001"; state := 8; WHEN 8 => address_in <= 6; instr <= "0000000000000000"; state := 9; WHEN 9 => load <= '0'; start <= '1'; reset <= '1'; state := 10; WHEN 10 => start <= '0'; reset <= '0'; state := 11; WHEN OTHERS => END CASE; END PROCESS; END beh_test_file1; CONFIGURATION config_file1 OF test_file1 IS FOR beh_test_file1 FOR u1: basic_comp USE ENTITY work.basic_comp; END FOR; END FOR; END config_file1;