fg_05_01.vhd entity program_ROM -- analyzed, syntax test only, formatted tb_05_01.vhd entity and_or_inv -- analyzed, tested ok fg_05_02.vhd architecture primitive of and_or_inv -- analyzed, tested ok, formatted tb_05_02.vhd entity tb_05_02 architecture test of tb_05_02 -- analyzed, tested ok fg_05_03.vhd entity fg_05_03 architecture test of fg_05_03 -- analyzed, tested ok, formatted fg_05_04.vhd entity fg_05_04 architecture test of fg_05_04 -- analyzed, tested ok, formatted fg_05_05.vhd entity edge_triggered_Dff architecture behavioral of edge_triggered_Dff -- analyzed, tested ok, formatted tb_05_03.vhd entity tb_05_03 architecture test of tb_05_03 -- analyzed, tested ok fg_05_06.vhd entity mux2 architecture behavioral of mux2 -- analyzed, tested ok, formatted tb_05_04.vhd entity tb_05_04 architecture test of tb_05_04 -- analyzed, tested ok fg_05_07.vhd entity fg_05_07 architecture test of fg_05_07 -- analyzed, tested ok, formatted fg_05_08.vhd entity fg_05_08 architecture test of fg_05_08 -- analyzed, tested ok, formatted fg_05_09.vhd entity computer_system architecture abstract of computer_system -- analyzed, tested ok, formatted fg_05_12.vhd entity fg_05_12 architecture test of fg_05_12 -- analyzed, tested ok, formatted fg_05_16.vhd entity and2 architecture detailed_delay of and2 -- analyzed, tested ok, formatted tb_05_05.vhd entity tb_05_05 architecture test of tb_05_05 -- analyzed, tested ok pk_test.vhd package stimulus_generators package body stimulus_generators -- analyzed, tested ok fg_05_17.vhd entity fg_05_17 architecture test of fg_05_17 -- analyzed, tested ok, formatted fg_05_18.vhd entity fg_05_18 architecture test of fg_05_18 -- analyzed, tested ok, formatted fg_05_19.vhd entity fg_05_19 architecture test of fg_05_19 -- analyzed, tested ok, formatted fg_05_20.vhd entity fg_05_20 architecture test of fg_05_20 -- analyzed, tested ok, formatted fg_05_21.vhd entity half_adder architecture truth_table of half_adder -- analyzed, tested ok, formatted fg_05_22.vhd entity S_R_flipflop architecture functional of S_R_flipflop -- analyzed, tested ok, formatted tb_05_06.vhd entity tb_05_06 architecture test of tb_05_06 -- analyzed, tested ok fg_05_23.vhd entity S_R_flipflop -- analyzed, tested ok, formatted tb_05_07.vhd architecture functional of S_R_flipflop entity tb_05_07 architecture test of tb_05_07 -- analyzed, tested ok fg_05_24.vhd entity ROM -- analyzed, tested ok, formatted tb_05_08.vhd architecture do_nothing of ROM entity tb_05_08 architecture test of tb_05_08 -- analyzed, tested ok fg_05_25.vhd entity reg4 architecture struct of reg4 -- analyzed, tested ok, formatted tb_05_09.vhd entity tb_05_09 architecture test of tb_05_09 -- analyzed, tested ok tb_05_10.vhd entity add_1 architecture boolean_eqn of add_1 entity buf4 architecture basic of buf4 package counter_types -- analyzed, tested ok fg_05_27.vhd entity counter architecture registered of counter -- analyzed, tested ok, formatted tb_05_11.vhd entity tb_05_10 architecture test of tb_05_10 -- analyzed, tested ok fg_05_28.vhd entity register entity microprocessor architecture RTL of microprocessor -- analyzed, syntax test only, formatted tb_05_12.vhd entity in_pad entity reg32 entity adder -- analyzed, syntax test only fg_05_30.vhd architecture cell_based of filter -- analyzed, syntax test only, formatted tb_05_13.vhd package tb_05_13 -- analyzed, syntax test only ch_05_01.vhd entity adder -- analyzed, syntax test only, formatted ch_05_02.vhd entity adder -- analyzed, syntax test only, formatted ch_05_03.vhd entity and_or_inv -- analyzed, syntax test only, formatted ch_05_04.vhd entity top_level -- analyzed, syntax test only, formatted ch_05_05.vhd architecture abstract of adder -- analyzed, syntax test only, formatted ch_05_06.vhd entity ch_05_06 architecture test of ch_05_06 -- §5.3_a, §5.3_b -- analyzed, tested ok, formatted ch_05_07.vhd entity ch_05_07 architecture test of ch_05_07 -- §5.3_c, §5.3_d, §5.3_e -- analyzed, tested ok, formatted ch_05_08.vhd entity ch_05_08 architecture test of ch_05_08 -- §5.3_f, §5.3_g -- analyzed, tested ok, formatted ch_05_09.vhd entity ch_05_09 architecture test of ch_05_09 -- §5.3_h, §5.3_i, §5.3_j, §5.3_k -- analyzed, tested ok, formatted ch_05_10.vhd entity ch_05_10 architecture test of ch_05_10 -- §5.3_l -- analyzed, tested ok, formatted ch_05_11.vhd entity ch_05_11 architecture test of ch_05_11 -- analyzed, tested ok, formatted ch_05_12.vhd entity ch_05_12 architecture test of ch_05_12 -- §5.3_m, §5.3_n -- analyzed, tested ok, formatted ch_05_13.vhd entity ch_05_13 architecture test of ch_05_13 -- §5.3_o -- analyzed, tested ok, formatted ch_05_14.vhd entity ch_05_14 architecture test of ch_05_14 -- §5.3_p, §5.3_q -- analyzed, tested ok, formatted ch_05_15.vhd entity ch_05_15 architecture test of ch_05_15 -- §5.3_r, §5.3_s -- analyzed, tested ok, formatted ch_05_16.vhd entity ch_05_16 architecture test of ch_05_16 -- §5.3_t -- analyzed, tested ok, formatted ch_05_17.vhd entity ch_05_17 architecture test of ch_05_17 -- analyzed, tested ok, formatted ch_05_18.vhd entity DRAM_controller architecture fpld of DRAM_controller entity ch_05_18 architecture test of ch_05_18 -- §5.4_a, §5.4_b -- analyzed, tested ok, formatted ch_05_19.vhd package ch_05_19 -- analyzed, syntax test only, formatted ch_05_20.vhd package pk_05_20 entity FIFO entity ch_05_20 architecture test of ch_05_20 -- analyzed, syntax test only, formatted ch_05_21.vhd entity and_gate architecture behavioral of and_gate entity ch_05_21 architecture test of ch_05_21 -- analyzed, tested ok, formatted ch_05_22.vhd entity mux4 architecture functional of mux4 entity ch_05_22 architecture test of ch_05_22 -- analyzed, tested ok, formatted ch_05_23.vhd entity and_or_inv architecture functional of and_or_inv entity ch_05_23 architecture test of ch_05_23 -- analyzed, tested ok, formatted ch_05_24.vhd entity and3 architecture functional of and3 entity ch_05_24 architecture test of ch_05_24 -- analyzed, tested ok, formatted ch_05_25.vhd entity mux4 architecture functional of mux4 entity ch_05_25 architecture test of ch_05_25 -- VHDL-87, analyzed, tested ok, formatted ch_05_26.vhd entity ch_05_26 architecture test of ch_05_26 -- analyzed, syntax test only, formatted ch_05_27.vhd entity ch_05_27 architecture test of ch_05_27 -- analyzed, syntax test only, formatted