|PJRC.COM Offline Archive, February 07, 2004
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The E signal is an active high enable, which is asserted when
the processor makes a memory access within the address range of
0xFE00 to 0xFEFF. RS and R/W are control lines for the
display. In order to meet the timing requirements for all standard
LCD displays, these are connected to the processor's address lines
so they are asserted and remain stable while E is asserted.
Because of this, separate locations are used to read and write to the
LCD. See the memory map page for
The P1.0 through P1.7 are connected directly to
the 87C52's port #1. These pins are the easiest to use as
single bits. In assembly, they are written using "CLR P1.4"
or "SETB P1.4", and they are read using "MOV C, P1.4" (moves
the bit value into the carry bit). In C (using SDCC, with
#include <8051.h>), they are accessed using names such as "P1_4".
if (!P1_3) printf("pin P1.3 is low");
The 8051 port pins are quasi-bidirectional, which essentially
means that you must write a 1 (which is the default) to the pin
to cause it to act as an input.
Signals INT0 and INT1 connect to the 87C52's two interrupt pins. The 87C52 can be configured to execute and interrupt routine associated with each pin when it is low or when a falling edge occurs. In the low level sensitive setting, the interrupt service code usually takes some action which causes the hardware to stop driving the pin low, so that another interrupt does not immediately occur when the interrupt service code returns to the main program. If interrupt are not enabled, these pins can be accessed as ordinary P3.2 and P3.3 port pins. INT1 is also connected to the SINGLE STEP jumper and will be shorted to ground if that jumper is installed.
PA.0 to PA.7, PB.0 to PB.7, and PC.0 to PC.7 are connected to a 82C55 chip mapped at 0xF800. PD.0 to PD.7 and PF.0 to PF.7 are connected to a second 82C55 chip mapped at 0xF900, and they correspond to ports A and C on that second chip, but that second chips ports are labeled D, E, and F to avoid confusion with the ports from the first 82C55 chip (port E connects to the 8 LEDs). Each 82C55 chip is controlled with 4 memory mapped locations, one to read or write each 8-bit port, and a 4th register to configure the 82C55 chip. See the memory map page for details. The 82C55 must first be configured by writing a byte to its config register, and then the three locations which access the ports may be used.
The FLASH ERASE jumper causes T1 (also P3.5, pin 17 on the 82C52) to be shorted to ground. During normal operation, this does not erase the flash. When PAULMON2 boots, it reads this pin and if it remains shorted for 256 consecutive reads, the PAULMON2 will erase the flash rom chip. Normally the flash rom is erased from the PAULMON2 menu using the 'Z' command. However, if you have loaded a program into the flash rom and used and "auto-start" header on it, PAULMON2 will jump to your code instead of presenting the normal menus on the serial port. If your code does not return back to the monitor, then you will be unable to get to the normal PAULMON2 menus and this pin will allow you to erase the chip you can can return to the menus and download a new version of your program.
The SINGLE STEP jumper shorts the INT1 interrupt pin to
ground. This is required to use PAULMON2's single-step feature.
The single-step operates by enabling interrupt #1 and using the
8051's feature where 1 instruction is always executed after and
interrupt. This can be a nice way to "see" your code run,
particularly if you are learning assembly. Due to the interrupt
usage, it is rarely useful for debugging sophisticated applications.
The WR and RD signals are active low strobes for write and read. WR is connected directly to the 87C52's WR pin, but RD is connected to the 74AC08 AND gate. RD is asserted low with either the 87C52's PSEN or RD signal is asserted. This means that either MOVX or MOVC may be used to read your connected peripheral chips. Some peripheral chips call their read pin OE (output enable). Typically, the RD pin can connect directly to the peripheral's OE pin.
Four chip select signals, CS2, CS3, CS4,
and CS5 are provided to allow easy connection of most
bus-style peripheral chips. Each of these signals is asserted
low when and access is made within its 256 byte range. See
the memory map page for details.
Though the printed maximum voltage is only 12 volts, the board can actually accept up to 30 volts DC. Higher voltages will cause the 7805 voltage regulator to become hot. The 7805 includes automatic thermal shutdown, but it can become very hot before this upper limit is reached, so caution should be observed if a higher input voltage is used.
The board requires approximately 50 mA when executing code from
the flash rom and communicating with a PC on the serial port.
Each LED adds about 4 mA. If a LCD with a backlight
is used, the backlight will consume considerable current. The
16x2 LCD from PJRC
uses approximately 250 mA for its backlight. Additional current
also causes the 7805 to heat up, so the board should not be run
with more than 12 volts if a LCD backlight is used.