2051 Microcontroller

AT40K20-2DQC ATMEL  - FPGA

AT40K20 DSP optimized FPGA with free RAM, Flexible Single/Dual Port, Sync/Async 10 ns SRAM, 8 Global Clock, 20K - 30K Usable Gates, 256 I/O's, 1024 Cells and 8192 RAM Bits

 

What is the 2051 microcontroller?


The 2051 is a 20 pin version of the 8051. It is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K bytes of Flash programmable and erasable read only memory. Atmel manufactures the chip using high-density nonvolatile memory technology. The 2051 and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel 2051 is a powerful microcontroller. It provides a very flexible, cost-effective solution to many embedded control applications.

 

Operational features of the 2051

The 2051 features Compatibility with MCS-51 ™ Products, 2K Bytes of Reprogrammable Flash Memory with 1,000 Write/Erase Cycles. The operating range of the 2051 is 2.7V to 6V. Among these features, the 2051 also contains the following features:

  • Fully Static Operation: 0 Hz to 24 MHz
  • Two-level Program Memory Lock
  • 128 x 8-bit Internal RAM
  • 15 Programmable I/O Lines
  • Two 16-bit Timer/Counters
  • Six Interrupt Sources
  • Programmable Serial UART Channel
  • Direct LED Drive Outputs
  • On-chip Analog Comparator
  • Low-power Idle and Power-down Modes

 

 

2051 Pin-out and Description

 


Pin Description

 

Pin Name:                                       Purpose:

VCC                                                               Supplies voltage and power.

 

GND                                                               Ground.

 

Port 1                                                              Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 toP1.7 provide internal pull-ups. P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pull-ups. Port 1 also receives code data during Flash programming and verification.

 

Port 3                                                              Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20mA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C2051 as listed below:

                                                                       

Port 3 also receives some control signals for Flash programming and verification.

 

RST                                                                Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device.

 

Restrictions on Instructions

 

The AT89C2051 and is the economical and cost-effective member of Atmel’s family of microcontrollers. Therefore, it contains only 2K bytes of flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should

 

 

 

 

be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H

would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not.

 

1. Branching instructions:

 

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR

 

These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown program behavior.

 

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ

 

With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution.

 

For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved.

 

2. MOVX-related instructions, Data Memory:

 

The 2051 contains 128 bytes of internal data memory. Thus, in the 2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA

memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions,

even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly.

 

 

 

 

 

BLOCK DIAGRAM OF 2051

 

Power-down Mode

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Registers

retain their values until the power down mode is

terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and stabilize.

 

P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used.

The 2051 is a low voltage (2.7V - 6V), high performance CMOS 8-bit microcontroller with 2 Kbytes of Flash programmable and erasable read only memory (PEROM). This device is compatible with the industry standard 8051 instruction set and pin-out. The 2051 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. 
 
In addition, the 2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

 

 

Uses of the 2051 Microcontroller:

 

The 2051 is used in many applications.

 

·        Controlling 7-segment displays

-         Clocks

-         Timers

 

 

 

·        Sensor projects

-         Temperature

-         Light

 

·        Used to Control LCD ( 8051 )

 

 

 

 

 

 

 

 

 

 

 

 

Digital Thermometer

 

·        Robotics

 

Digital Clock Using Four 7-Segment Displays
Using 8051 RAM (The Game of Simon)
Non Volatile RAM Memory - EEPROM
Light Sensor Project
Temperature Sensor Project
Using the LCD Module
Pulse Width Modulation
LCD Instruction Set
Data Collection - Analog to Digital Conversion and Communicating with a PC through the Serial Port
MIDI Controller

============================================================